HD151011
Dual BCD Programmable Counter
with Synchronous Preset Enable
ADE-205-100(Z)
Rev 0
April 1995
The HD151011 has BCD decimal two digits down counter and D-type Flip Flop. The counter can set up to
max 99 counts and synchronous preset (SPE) input can preset the data. When the count value is 0, the next
clock pulse presets the data to invert the output. D-type Flip Flop takes the counter output as clock pulse,
whose data is transferred to output at the rise edge. It is applied to generate AC signal for STN type liquid
crystal and general-use divider.
Features
•
High speed operation
tpd (CLK or
CLK
to Q) = 35 ns (typ)
•
High output current
Fanout of 10 LS TTL Loads
•
Wide operating voltage
Vcc = 2 to 6 V
•
Low supply current (Ta = 25°C)
Icc (Static) = 4
µA
(max)
HD151011
Function Table
Control Inputs
CLR
H
X
—
—
L
H
PR
H
X
—
—
H
L
SPE
H
L
—
—
—
—
C/T
X
X
H
L
—
—
Mode
Generally count
Synchronous preset
—
—
Initialize of Q output
Initialize of Q output
Operation Description
Down count at the rise edge of clock (CLK),
Down count at the fall edge of clock (CLK)
Jn data is preset at the rise of clock (CLK),
the fall of clock (CLK)
Clock inputs (CLK,
CLK)
is CMOS level
Clock inputs (CLK,
CLK)
is TTL level
Initialize of Q = "L"
Initialize of Q = "H"
H: High level
L: Low level
Z: Immaterial
—: Irrespective of condition
1. Synchronous preset (SPE) input can set max 99 down counts.
2. When the count value is 0, the next clock pulse presets the data to invert the output.
3. CLR and PR inputs initialize output state.
4. Clock inputs (CLK,
CLK)
is selectable CMOS level (V
CC
= 2.0 to 6.0 V) and TTL level (V
CC
= 4.5 to 5.5V)
(Jn, C/T, PR, CLR and
SPE
inputs are CMOS level)
Note: Don't set data exceeding 99 to Jn. (J0: LSB, J7: MSB)
2
HD151011
Pin Arrangement
CO 1
J0 2
J1 3
J2 4
J3 5
J4 6
J5 7
J6 8
J7 9
GND 10
20 V
CC
19 (Test 1)*
18 (Test 2)*
17 C / T
16 CLK
15 CLK
14 Q
13 PR
12 SPE
11 CLR
(Top view)
* Pins 18 and 19 are for function test only and should be open.
Pin Description
Pin Name
Input pins
J0 to J7
C/T
CLK,
CLK
SPE
PR
CLR
Output pins
CO
Q
Pin Description
Count data input for option
Level change input for CLK,
CLK
(CMOS level or TTL level)
Clock inputs
CLK : Rise edge trigger
CLK
: Fall edge trigger
Preset input for Jn data
Preset input for D-type Flip Flop (Initialize "L" at Q output)
Clear input for D-type Flip Flop (Initialize "H" at Q output)
Output for BCD decimal counter
Output for D-type Flip Flop
3
HD151011
Absolute Maximum Ratings
Item
Supply voltage
Input / output voltage
VCC, GND current
Output current / pin
Power dissipation
Storage temperature
Input diode current
Output diode current
Symbol
V
CC
V
IN
/ V
OUT
I
CC
, I
GND
I
OUT
P
T
Tstg
I
IK
I
OK
Ratings
–0.5 to 7.0
–0.5 to V
CC
+0.5
±50
±25
757
–65 to 150
±20
±20
Unit
V
V
mA
mA
mW
°C
mA
mA
Notes: 1. The absolute maximum ratings are values which must not individually be exceeded, and
furthermore, no two of which may be realized at the same time.
2. All voltage values except for differential input voltage are with respect to network ground
terminal.
Recommended Operating Conditions
Item
Supply voltage
Input / output voltage
Operating temperature
Input rise / fall time
*1
V
CC
= 2.5 V
V
CC
= 4.5 V
V
CC
= 5.5 V
Note:
Symbol
V
CC
V
IN
/
Topr
tr, tf
OUT
Min
2
0
–40
0
0
0
Typ
—
—
—
—
—
—
Max
6
V
CC
+85
1000
500
400
Unit
V
V
°C
ns
1. This item guarantees maximum limit when one input switches.
4
HD151011
Logic Diagram
C/T
J0
J1
J2
J3
J4
J5
J6
J7
J0
BCD decimal counter
J1
J2
J3
J4
J5
J6
J7
CLK
CLK
CLK
CO
PR
PR
D
CO
SPE
CK
CLR
SPE
CLR
Q
Q
Q
5
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