MD82C50A-5B datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > semiconductor> The embedded processor and controller> MD82C50A-5B

Preview

MD82C50A-5B: Description1 CHANNEL(S), 625K bps, SERIAL COMM CONTROLLER, CDIP40; Categorysemiconductor The embedded processor and controller; File Size107KB，21 Pages; ManufacturerIntersil ( Renesas ); Websitehttp://www.intersil.com/cda/home/

Download Datasheet Compare View All

MD82C50A-5B Overview

1 CHANNEL(S), 625K bps, SERIAL COMM CONTROLLER, CDIP40

Preview

Download Datasheet

View All

82C50A

March 1997

CMOS Asynchronous

Communications Element

Description

The 82C50A Asynchronous Communication Element (ACE)

is a high performance programmable Universal Asynchro-

nous Receiver/Transmitter (UART) and Baud Rate Genera-

tor (BRG) on a single chip. Using Intersil’s advanced Scaled

SAJI IV CMOS Process, the ACE will support data rates

from DC to 625K baud (0-10MHz clock).

The ACE’s receiver circuitry converts start, data, stop, and

parity bits into a parallel data word. The transmitter circuitry

converts a parallel data word into serial form and appends

the start, parity, and stop bits. The word length is program-

mable to 5, 6, 7, or 8 data bits. Stop bit selection provides a

choice of 1,1.5, or 2 stop bits.

The Baud Rate Generator divides the clock by a divisor

programmable from 1 to 2

-1 to provide standard RS-232C

baud rates when using any one of three industry standard

baud rate crystals (1.8432MHz, 2.4576MHz, or 3.072MHz).

A programmable buffered clock output (BAUDOUT) provides

either a buffered oscillator or 16X (16 times the data rate)

baud rate clock for general purpose system use.

To meet the system requirements of a CPU interfacing to an

asynchronous channel, the modem control signals RTS,

CTS, DSR, DTR, RI, DCD are provided. Inputs and outputs

have been designed with full TTL/CMOS compatibility in

order to facilitate mixed TTL/NMOS/CMOS system design.

Features

•

Single Chip UART/BRG

DC to 625K Baud (DC to 10MHz Clock)

Crystal or External Clock Input

On Chip Baud Rate Generator 1 to 65535 Divisor

Generates 16X Clock

Prioritized Interrupt Mode

Fully TTL/CMOS Compatible

Microprocessor Bus Oriented Interface

80C86/80C88 Compatible

Scaled SAJI IV CMOS Process

Low Power - 1mA/MHz Typical

Modem Interface

Line Break Generation and Detection

Loopback and Echo Modes

Doubled Buffered Transmitter and Receiver

Single 5V Supply

Ordering Information

PACKAGE

PDIP

PLCC

CERDIP

TEMPERATURE

RANGE (

0 to +70

-40 to +85

0 to +70

-40 to +85

0 to +70

-40 to +85

-55 to +125

625K BAUD

CP82C50A-5

IP82C50A-5

CS82C50A-5

IS82C50A-5

CD82C50A-5

ID82C50A-5

MD82C50A-5/B

PKG.

NO.

E40.6

N44.65

F40.6

Functional Diagram

CSO

CS1

CS2

ADS

DISTR

LINE STATUS

AND CONTROL

INTERRUPT

ENABLE,

ID, & CONTROL

MICROPROCESSOR INTERFACE

CSOUT

DDIS

INTRPT

UART

RECEIVER

DIVISOR LATCH

AND BAUD RATE

GENERATOR

TRANSMITTER

MODEM

MODEM CONTROL

MODEM STATUS

SIN

RCLK

XTAL1

XTAL2

SOUT

RTS

DTR

OUT1

OUT2

CTS

DSR

DCD

15 BAUDOUT

DOSTR 19

DOSTR 18

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207

Intersil Corporation 1999

File Number

2958.1

82C50A

Pin Description

SYMBOL

RTS

NUMBER

(Continued)

ACTIVE

LEVEL

TYPE

DESCRIPTION

REQUEST TO SEND: The RTS signal is an output used to enable the modem. The

RTS pin is set low by writing a logic 1 to MCR (1) bit 1 of the Modem Control Regis-

ter. The RTS pin is reset high by Master Reset. When ACTIVE, the RTS pin indicates

to the DCE that the 82C50A has data ready to transmit. In half duplex operations,

RTS is used to control the direction of the line.

BAUDOUT: This output is a 16X clock out used for the transmitter section (16X =

16 times the data rate). The BAUDOUT clock rate is equal to the reference oscillator

frequency divided by the speciﬁed divisor in the Baud Rate Generator Divisor Latch-

es DLL and DLM. BAUDOUT may be used by the Receiver section by tying this out-

put to RCLK.

BAUDOUT

OUT1

OUTPUT 1: This is a general purpose output that can be programmed ACTIVE

(low) by settingVCR(2) (OUT1) of the Modem Control Register to a high level. The

OUT1 pin is set high by Master Reset. The OUT1 pin is INACTIVE (high) during loop

mode operation.

OUTPUT 2: This is a general purpose output that can be programmed ACTIVE

(low) by setting MCR(3) (OUT1) of the Modem Control Register to a high level. The

OUT2 pin is set high by Master Reset. The OUT2 signal is INACTIVE (high) during

loop mode operation.

RING INDICATOR: When low, RI indicates that a telephone ringing signal has been

received by the modem or data set. The RI signal is a modem control input whose

condition is tested by reading MSR(6) (RI). The Modem Status Register output TERI

(MSR(2)) indicates whether the RI input has changed from a Low to High since the

previous reading of the MSR. If the interrupt is enabled (IER (3) = 1) and RI changes

from a Low to High, an interrupt is generated. The ACTIVE (low) state of RI indicates

that the DCE is receiving a ringing signal. RI will appear ACTIVE for approximately

the same length of time as the ACTIVE segment of the ringing cycle. The INACTIVE

state of RI will occur during the INACTIVE segments not detected by the DCE. This

circuit is not disabled by the INACTIVE condition of DTR.

DATA CARRIER DETECT: When ACTIVE (low), DCD indicates that the data carrier

has been detected by the modem or data set. DCD is a modem input whose condi-

tion can be tested by the CPU by reading MSR(7) (DCD) of the Modem Status Reg-

ister. MSR(3) (DDCD) of the Modem Status Register indicates whether the DCD

input has changed since the previous reading of the MSR. DOD has no effect on the

receiver. If the DCD changes state with the modem status interrupt enabled, an in-

terrupt is generated.

When DCD is ACTIVE (low), the received line signal from the remote terminal is

within the limits speciﬁed by the DCE manufacturer. The INACTIVE (high) signal in-

dicates that the signal is not within the speciﬁed limits, or is not present.

OUT2

DCD

MASTER RESET: The MR input forces the 82C50A into an idle mode in which all

serial data activities are suspended. The Modem Control Register (MCR) along with

its associated outputs are cleared. The Line Status Register (LSR) is cleared except

for the THRE and TEMT bits, which are set. The 82C50A remains in an idle state

until programmed to resume serial data activities. The MR input is a Schmitt trigger

input. See the DC Electrical Characteristics for Schmitt trigger logic input voltage

levels. See Table 7 for a summary of Master Reset’s effect on 82C50A operation.

INTERRUPT REQUEST: The lNTRPT output goes ACTIVE (high) when one of the

following interrupts has an ACTIVE (high) condition and is enabled by the Interrupt

Enable Register: Receiver Error ﬂag, Received Data Available, Transmitter Holding

vice or a MR operation. See Figure 1. Interrupt Control Structure.

SERIAL DATA INPUT: The SIN input is the serial data input from the communication

line or modem to the 82C50A receiver circuits. A mark (1) is high, and a space (0)

is low. Data inputs on SIN are disabled when operating in the loop mode.

lNTRPT

SIN

MD82C50A-5B Related Products

	MD82C50A-5B	ID82C50A	82C50	CD82C50A-5	MD82C50A-5	ID82C50A-5	IP82C50A-5
Description	1 CHANNEL(S), 625K bps, SERIAL COMM CONTROLLER, CDIP40	1 CHANNEL(S), 625K bps, SERIAL COMM CONTROLLER, CDIP40	1 CHANNEL(S), 625K bps, SERIAL COMM CONTROLLER, CDIP40	1 CHANNEL(S), 625K bps, SERIAL COMM CONTROLLER, CDIP40	1 CHANNEL(S), 625K bps, SERIAL COMM CONTROLLER, CDIP40	1 CHANNEL(S), 625K bps, SERIAL COMM CONTROLLER, CDIP40	1 CHANNEL(S), 625K bps, SERIAL COMM CONTROLLER, PDIP40

Recommended Resources

Application circuit b of TDA1519

Add a timer circuit to the radio

Sound-activated thermometer circuit with analog input

Biogas detection alarm

Calibration signal generator circuit

6OXT(1.0) computer motherboard circuit diagram_20

Questions about infrared decoding: I have implemented infrared decoding using the delay method, but for some reason, the pulse count obtained by counting with TIMER1 is not working. After analyzing the serial output, I feel that there ...; wateras1 RF/Wirelessly

See who's talking big: This idea is probably not difficult to implement, but I still use a black and white screen phone, haha, I will try it on a tablet later. If this idea can be implemented, I think it will become a game ...; fsyicheng Wireless Connectivity

Goodbye 2019, hello 2020, live up to your youth: # Goodbye 2019, hello 2020. I muster up the courage to make a post to summarize and look forward to the future. 2019 was the most difficult year, but also the happiest year. The difficulty was due to ...; hotsauce1861 Talking

USB Circuit Protection Design Solution: PPTC (Poly-Positive Temperature Coefficient) devices are a reliable and economical solution for current overload protection of computers and related devices. Since these devices are available in a var...; fighting Analog electronics

Why can't the acceptance letter of usart communication work?: There is no problem with sending usart messages, but receiving messages is not working. Could any senior help me take a look? Thanks! #include pic.h#include "delay.h"#include stdio.h#include "lcd.h" _...; eeleader MCU

Share the algorithm operation time measurement of TMS320C66x: [size=4]The two most commonly used methods for measuring algorithm running time during TI CCS platform DSP development. One is more convenient to use in projects with SYS/BIOS system, and the other is...; Aguilera Microcontroller MCU

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components