HD6435328F datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> HD6435328F

HD6435328F: DescriptionManual Gives a Hardware Description; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，459 Pages; ManufacturerHitachi （Renesas ）; Websitehttp://www.renesas.com/eng/

Download Datasheet Parametric Compare View All

HD6435328F Overview

Manual Gives a Hardware Description

HD6435328F Parametric

Parameter Name	Attribute value
Maker	Hitachi （Renesas ）
Parts packaging code	QFP
package instruction	PLASTIC, QFP-80
Contacts	80
Reach Compliance Code	unknow
Has ADC	YES
Other features	CAPTURE/COMPARE UNIT; 2V DATA RETENTION
Address bus width	20
bit size	8
boundary scan	NO
maximum clock frequency	10 MHz
DAC channel	NO
DMA channel	NO
External data bus width	8
Format	FIXED POINT
Integrated cache	NO
JESD-30 code	S-PQFP-G80
length	14 mm
low power mode	YES
Number of DMA channels
Number of external interrupt devices	3
Number of I/O lines	65
Number of serial I/Os	1
Number of terminals	80
Number of timers	2
On-chip data RAM width	8
On-chip program ROM width	8
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Package shape	SQUARE
Package form	FLATPACK
Certification status	Not Qualified
RAM (number of words)	512
rom(word)	32768
ROM programmability	MROM
Maximum seat height	3.05 mm
speed	10 MHz
Maximum slew rate	50 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
width	14 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER

Preview

Download Datasheet

View All

H8/532 Hardware Manual

Contents

Section 1 Overview

1.1

1.2

1.3

Features ··································································································································1

Block Diagram ·······················································································································4

Pin Arrangements and Functions ···························································································5

1.3.1 Pin Arrangement ·········································································································5

1.3.2 Pin Functions ··············································································································8

Section 2 MCU Operating Modes and Address Space

2.1

2.2

2.3

Overview ······························································································································23

Mode Descriptions ···············································································································24

Address Space Map ··············································································································25

2.3.1 Page Segmentation ····································································································25

2.3.2 Page 0 Address Allocations ······················································································27

Mode Control Register (MDCR) ·························································································29

2.4

Section 3 CPU

3.1

Overview ······························································································································31

3.1.1 Features ·····················································································································31

3.1.2 Address Space ···········································································································32

3.1.3 Register Configuration ······························································································33

CPU Register Descriptions ··································································································34

3.2.1 General Registers ······································································································34

3.2.2 Control Registers ······································································································35

3.2.3 Initial Register Values ·······························································································40

Data Formats ························································································································41

3.3.1 Data Formats in General Registers ···········································································41

3.3.2 Data Formats in Memory ··························································································42

Instructions ···························································································································44

3.4.1 Basic Instruction Formats ·························································································44

3.4.2 Addressing Modes ····································································································45

3.4.3 Effective Address Calculation ···················································································47

Instruction Set ······················································································································50

3.5.1 Overview ···················································································································50

3.5.2 Data Transfer Instructions ·························································································52

3.5.3 Arithmetic Instructions ·····························································································53

3.5.4 Logic Operations ·······································································································54

3.5.5 Shift Operations ········································································································55

3.5.6 Bit Manipulations ······································································································56

3.5.7 Branching Instructions ······························································································57

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

3.5.8 System Control Instructions ······················································································59

3.5.9 Short-Format Instructions ·························································································62

Operating Modes ··················································································································62

3.6.1 Minimum Mode ········································································································62

3.6.2 Maximum Mode ········································································································63

Basic Operational Timing ····································································································63

3.7.1 Overview ···················································································································63

3.7.2 On-Chip Memory Access Cycle ···············································································64

3.7.3 Pin States during On-Chip Memory Access ·····························································65

3.7.4 Register Field Access Cycle (Addresses H'FF80 to H'FFFF) ···································66

3.7.5 Pin States during Register Field Access (Addresses H'FF80 to H'FFFF) ·················67

3.7.6 External Access Cycle ·······························································································68

CPU States ···························································································································69

3.8.1 Overview ···················································································································69

3.8.2 Program Execution State ···························································································71

3.8.3 Exception-Handling State ·························································································71

3.8.4 Bus-Released State ····································································································72

3.8.5 Reset State ·················································································································77

3.8.6 Power-Down State ····································································································77

Programming Notes ·············································································································78

3.9.1 Restriction on Address Location ···············································································78

3.9.2 Note on MULXU Instruction·····················································································79

Section 4 Exception Handling

4.1

Overview ······························································································································81

4.1.1 Types of Exception Handling and Their Priority ······················································81

4.1.2 Hardware Exception-Handling Sequence ·································································82

4.1.3 Exception Factors and Vector Table ··········································································82

Reset ····································································································································85

4.2.1 Overview ···················································································································85

4.2.2 Reset Sequence ·········································································································85

4.2.3 Stack Pointer Initialization ························································································86

Address Error ·······················································································································89

4.3.1 Illegal Instruction Prefetch ························································································89

4.3.2 Word Data Access at Odd Address ···········································································89

4.3.3 Off-Chip Address Access in Single-Chip Mode ·······················································89

Trace ····································································································································90

Interrupts ······························································································································90

Invalid Instruction ················································································································92

Trap Instructions and Zero Divide ·······················································································92

Cases in Which Exception Handling is Deferred ·································································92

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.8.1 Instructions that Disable Interrupts ···········································································92

4.8.2 Disabling of Exceptions Immediately after a Reset ··················································93

4.8.3 Disabling of Interrupts after a Data Transfer Cycle ··················································93

4.9 Stack Status after Completion of Exception Handling ························································94

4.9.1 PC Value Pushed on Stack for Trace,

Interrupts, Trap Instructions, and Zero Divide Exceptions ·······································96

4.9.2 PC Value Pushed on Stack for Address Error and Invalid

Instruction Exceptions ······························································································96

4.10 Notes on Use of the Stack ····································································································96

Section 5 Interrupt Controller

5.1

Overview ······························································································································97

5.1.1 Features ·····················································································································97

5.1.2 Block Diagram ··········································································································98

5.1.3 Register Configuration ······························································································99

Interrupt Types ·····················································································································99

5.2.1 External Interrupts ····································································································99

5.2.2 Internal Interrupts ····································································································101

5.2.3 Interrupt Vector Table ·····························································································101

Register Descriptions ·········································································································103

5.3.1 Interrupt Priority Registers A to D (IPRA to IPRD) ···············································103

5.3.2 Timing of Priority Setting ·······················································································104

Interrupt Handling Sequence ·····························································································104

5.4.1 Interrupt Handling Flow ··························································································104

5.4.2 Stack Status after Interrupt Handling Sequence ·····················································107

5.4.3 Timing of Interrupt Exception-Handling Sequence ················································108

Interrupts During Operation of the Data Transfer Controller ············································108

Interrupt Response Time ····································································································111

5.2

5.3

5.4

5.5

5.6

Section 6 Data Transfer Controller

6.1

Overview ····························································································································113

6.1.1 Features ···················································································································113

6.1.2 Block Diagram ········································································································113

6.1.3 Register Configuration ····························································································114

Register Descriptions ·········································································································115

6.2.1 Data Transfer Mode Register (DTMR) ···································································115

6.2.2 Data Transfer Source Address Register (DTSR) ····················································116

6.2.3 Data Transfer Destination Register (DTDR) ·························································116

6.2.4 Data Transfer Count Register (DTCR) ···································································116

6.2.5 Data Transfer Enable Registers A to D (DTEA to DTED) ·····································117

Data Transfer Operation ·····································································································118

6.2

6.3

HD6435328F Related Products

	HD6435328F	HD6435328	HD6435328CP	HD6475328CP	HD6475328CG	HD6475328F
Description	Manual Gives a Hardware Description	Manual Gives a Hardware Description	Manual Gives a Hardware Description	Manual Gives a Hardware Description	Manual Gives a Hardware Description	Manual Gives a Hardware Description
Maker	Hitachi （Renesas ）	-	Hitachi （Renesas ）	Hitachi （Renesas ）	Hitachi （Renesas ）	Hitachi （Renesas ）
Parts packaging code	QFP	-	LCC	LCC	LCC	QFP
package instruction	PLASTIC, QFP-80	-	PLASTIC, LCC-84	QCCJ,	WQCCN,	PLASTIC, QFP-80
Contacts	80	-	84	84	84	80
Reach Compliance Code	unknow	-	unknown	unknow	unknow	unknow
Has ADC	YES	-	YES	YES	YES	YES
Other features	CAPTURE/COMPARE UNIT; 2V DATA RETENTION	-	CAPTURE/COMPARE UNIT; 2V DATA RETENTION	CAPTURE/COMPARE UNIT; 2V DATA RETENTION	CAPTURE/COMPARE UNIT; 2V DATA RETENTION	CAPTURE/COMPARE UNIT; 2V DATA RETENTION
Address bus width	20	-	20	20	20	20
bit size	8	-	8	8	8	8
boundary scan	NO	-	NO	NO	NO	NO
maximum clock frequency	10 MHz	-	10 MHz	10 MHz	10 MHz	10 MHz
DAC channel	NO	-	NO	NO	NO	NO
DMA channel	NO	-	NO	NO	NO	NO
External data bus width	8	-	8	8	8	8
Format	FIXED POINT	-	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT
Integrated cache	NO	-	NO	NO	NO	NO
JESD-30 code	S-PQFP-G80	-	S-PQCC-J84	S-PQCC-J84	S-GQCC-N84	S-PQFP-G80
length	14 mm	-	29.28 mm	29.28 mm	29.21 mm	14 mm
low power mode	YES	-	YES	YES	YES	YES
Number of external interrupt devices	3	-	3	3	3	3
Number of I/O lines	65	-	65	65	65	65
Number of serial I/Os	1	-	1	1	1	1
Number of terminals	80	-	84	84	84	80
Number of timers	2	-	2	2	2	2
On-chip data RAM width	8	-	8	8	8	8
On-chip program ROM width	8	-	8	8	8	8
Maximum operating temperature	85 °C	-	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-	-40 °C	-40 °C	-40 °C	-40 °C
PWM channel	YES	-	YES	YES	YES	YES
Package body material	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	CERAMIC, GLASS-SEALED	PLASTIC/EPOXY
encapsulated code	QFP	-	QCCJ	QCCJ	WQCCN	QFP
Package shape	SQUARE	-	SQUARE	SQUARE	SQUARE	SQUARE
Package form	FLATPACK	-	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER, WINDOW	FLATPACK
Certification status	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified
RAM (number of words)	512	-	512	512	1000	512
rom(word)	32768	-	32768	32768	32000	32768
ROM programmability	MROM	-	MROM	OTPROM	UVPROM	OTPROM
Maximum seat height	3.05 mm	-	4.6 mm	4.6 mm	4.03 mm	3.05 mm
speed	10 MHz	-	10 MHz	10 MHz	10 MHz	10 MHz
Maximum slew rate	50 mA	-	50 mA	50 mA	50 mA	50 mA
Maximum supply voltage	5.5 V	-	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage	4.5 V	-	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage	5 V	-	5 V	5 V	5 V	5 V
surface mount	YES	-	YES	YES	YES	YES
technology	CMOS	-	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	-	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	GULL WING	-	J BEND	J BEND	NO LEAD	GULL WING
Terminal pitch	0.65 mm	-	1.27 mm	1.27 mm	1.27 mm	0.65 mm
Terminal location	QUAD	-	QUAD	QUAD	QUAD	QUAD
width	14 mm	-	29.28 mm	29.28 mm	29.21 mm	14 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER	-	MICROCONTROLLER	MICROCONTROLLER	MICROCONTROLLER	MICROCONTROLLER
Base Number Matches	-	-	1	1	1	1

Recommended Resources

Heartbeat monitor circuit diagram

IRT1260 (TV and VCR) infrared remote control transmitter circuit

Practical circuit positive power supply circuit diagram

Power line carrier remote alarm circuit diagram

4-digit LED display driver UP, DOWN counter

555 sound and light control delay energy-saving light circuit

Error during eVC Build: An application targeting a Standard SDK for Windows CE.NET and build for the ARMV4 cpu cannot be run on the emulator device, in order to run this application on any cpu other than the emulator, you wi...; liujiang200612 Embedded System

Power Management Data Storage Device Selection: In data acquisition, data storage chips generally include RAM, E2PROM, FLASH and NVRAM. The following is a comparison of their advantages and disadvantages. (1) RAM (such as 62256, etc.) is also calle...; zbz0529 Power technology

How to choose operational amplifier in the front end of power system: In the design of front-end sampling in power systems, op amps are indispensable. This article mainly discusses the requirements for op amps in power systems and how to choose appropriate op amps.The s...; Jacktang Analogue and Mixed Signal

I want to ask how to release the memory resources of Compact C# pictures in WinCE.: Did you call dispose? It seems that the effect is not very obvious. It seems that you don't really call it. Can you really release it in the memory management in compact? Because the resource usage ex...; leoxmxiong Embedded System

How to start another exe program: How to start another exe program? I want to use C++ to make a program that starts another exe file. How can I do this?...; bobostart Embedded System

Dear masters, I have a 51 machine code disassembled source program (0000-3BFF), can you help to annotate and analyze it? Reward: Dear masters, I have a source program (0000-3BFF) of 51 machine code disassembly (it has been compiled under Weifu software). Can you help to annotate and analyze it? Reward, if you are interested, yo...; GUODAHUA 51mcu

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components