MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM72BA32/D
256KB and 512KB BurstRAM™
Secondary Cache Module for
Pentium™
The MCM72BA32SG and MCM72BA64SG are designed to provide a burst-
able, high performance, 256K/512K L2 cache for the Pentium microprocessor.
The modules are configured as 32K x 72 and 64K x 72 bits in a 136 pin dual read-
out single inline memory module (DIMM). The module uses four of Motorola’s
MCM67B518 or MCM67B618 BiCMOS BurstRAMs.
Bursts can be initiated with either address status processor (ADSP) or address
status controller (ADSC). Subsequent burst addresses are generated internal to
the BurstRAM by the burst advance (ADV) input pin.
Write cycles are internally self timed and are initiated by the rising edge of the
clock (K) input. Eight write enables are provided for byte write control.
The cache family is designed to interface with popular Pentium cache control-
lers with on board TAG.
PD0 – PD2 are reserved for density and speed identification.
•
Pentium–style Burst Counter on Board
•
Dual Readout SIMM for Circuit Density
•
Single 5 V
±
5% Power Supply
•
All Inputs and Outputs are TTL Compatible
•
Three State Outputs
•
Byte Parity
•
Byte Write Capability
•
Fast Module Clock Rates: 66 MHz, 60 MHz, 50MHz
•
Decoupling Capacitors for each Fast Static RAM
•
High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes
•
I/Os are 3.3 V Compatible
MCM72BA32
MCM72BA64
136–LEAD DIMM
CASE 1104–01
TOP VIEW
1
34
35
68
BurstRAM is a trademark of Motorola.
Pentium is a trademark of Intel Corp.
REV 2
5/95
©
Motorola, Inc. 1995
MOTOROLA FAST SRAM
MCM72BA32•MCM72BA64
1
PIN ASSIGNMENT
136–LEAD DIMM
TOP VIEW
PD2
VSS
VSS
VSS
VSS
PD1
NC
NC
VSS
VSS
PD0
NC
VSS
NC
VSS
Cache
Size
512KB
512KB
256KB
256KB
Module
72BA64SG66/60
72BA64SG50
72BA32SG66/60
72BA32SG50
PD0
PD1
DQ0
DQ1
VCC
DQ4
DQ6
DQP0
DQ8
DQ10
VSS
K0
VSS
DQ14
VCC
DQ16
DQ17
DQ19
DQ21
VCC
DQP2
DQ24
DQ26
DQ28
VSS
DQ31
DQP3
VSS
W0
W2
ADSP
ADV
VCC
W4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
VSS
PD2
VCC
DQ2
DQ3
DQ5
DQ7
VSS
DQ9
DQ11
DQ12
VSS
DQ13
DQ15
DQP1
VSS
DQ18
DQ20
DQ22
DQ23
VSS
DQ25
DQ27
DQ29
DQ30
VSS
E0
W1
W3
G0
ADSC
VSS
G1
W5
PIN NAMES
A0 – A15 . . . . . . . . . . . . . . . . . . . . . . Address Inputs
K0, K1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock
W0 – W7 . . . . . . . . . . . . . . . . . . . . . . . . . . Byte Write
E0, E1 . . . . . . . . . . . . . . . . . . . . . . . . Module Enable
G0, G1 . . . . . . . . . . . . . . . . . Module Output Enable
DQ0 – DQ63 . . . . . . . . . . Cache Data Input/Output
DQP0 – DQP7 . . . . . . . . . Data Parity Input/Output
ADSC . . . . . . . . . . . . . . Controller Address Status
ADSP . . . . . . . . . . . . . . . Processor Address Status
ADV . . . . . . . . . . . . . . . . . . . . . . . . . . Burst Advance
PD0 – PD2 . . . . . . . . . . . . . . . . . . Presence Detect
VCC . . . . . . . . . . . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
W6
DQ32
DQ33
VSS
DQ36
DQ38
DQ39
DQ40
VCC
DQ43
DQ45
DQ46
DQP5
VSS
K1
VSS
DQ52
DQ53
DQ55
DQP6
VCC
DQ58
DQ60
DQ62
DQP7
A0
A2
A4
A6
A8
A10
A12
A14
VSS
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
W7
E1
DQ34
DQ35
DQ37
VCC
DQP4
DQ41
DQ42
DQ44
VSS
DQ47
DQ48
DQ49
VSS
DQ50
DQ51
DQ54
DQ56
VSS
DQ57
DQ59
DQ61
DQ63
VCC
A1
A3
A5
A7
NC
A9
A11
A13
A15*
* This pin on the MCM72BA32 is a No Connect (NC)
MCM72BA32•MCM72BA64
2
MOTOROLA FAST SRAM
64K x 72 BurstRAM MEMORY MODULE BLOCK DIAGRAM
16
A0 – A15
ADSP
ADSC
ADV
K0
G0
E0
MCM67B618
A0 – A15
LW
8
ADSP
ADSC
ADV
K
G
E
DQ0 – DQ7
DQ8
UW
8
DQ9 – DQ16
DQ17
DQ8 – DQ15
DQP1
DQ0 – DQ7
DQP0
W1
W0
MCM67B618
A0 – A15
LW
8
ADSP
ADSC
ADV
K
G
E
DQ0 – DQ7
DQ8
UW
8
DQ9 – DQ16
DQ17
W2
DQ16 – DQ23
DQP2
W3
DQ24 – DQ31
DQP3
MCM67B618
A0 – A15
LW
8
ADSP
ADSC
ADV
K1
G1
E1
K
G
E
DQ0 – DQ7
DQ8
UW
8
DQ9 – DQ16
DQ17
W4
DQ32 – DQ39
DQP4
W5
DQ40 – DQ47
DQP5
MCM67B618
A0 – A15
LW
8
ADSP
ADSC
ADV
K
G
E
DQ0 – DQ7
DQ8
UW
8
DQ9 – DQ16
DQ17
W6
DQ48 – DQ55
DQP6
W7
DQ56 – DQ63
DQP7
MOTOROLA FAST SRAM
MCM72BA32•MCM72BA64
3
32K x 72 BurstRAM MEMORY MODULE BLOCK DIAGRAM
A15
A0 – A14
ADSP
ADSC
ADV
K0
G0
E0
15
NC
MCM67B518
A0 – A14
LW
8
ADSP
ADSC
ADV
K
G
E
DQ0 – DQ7
DQ8
UW
8
DQ9 – DQ16
DQ17
DQ8 – DQ15
DQP1
DQ0 – DQ7
DQP0
W1
W0
MCM67B518
A0 – A14
LW
8
ADSP
ADSC
ADV
K
G
E
DQ0 – DQ7
DQ8
UW
8
DQ9 – DQ16
DQ17
W2
DQ16 – DQ23
DQP2
W3
DQ24 – DQ31
DQP3
MCM67B518
A0 – A14
LW
8
ADSP
ADSC
ADV
K1
G1
E1
K
G
E
DQ0 – DQ7
DQ8
UW
8
DQ9 – DQ16
DQ17
W4
DQ32 – DQ39
DQP4
W5
DQ40 – DQ47
DQP5
MCM67B518
A0 – A14
LW
8
ADSP
ADSC
ADV
K
G
E
DQ0 – DQ7
DQ8
UW
8
DQ9 – DQ16
DQ17
W6
DQ48 – DQ55
DQP6
W7
DQ56 – DQ63
DQP7
MCM72BA32•MCM72BA64
4
MOTOROLA FAST SRAM
MCM67B618 BLOCK DIAGRAM
(See Note)
ADV
BURST LOGIC
Q0
BINARY
COUNTER
K
A0
16
Q1
A1
A1′
INTERNAL
ADDRESS
A0′
64K
×
18
MEMORY
ARRAY
ADSC
ADSP
CLR
2
A0 – A15
ADDRESS
REGISTER
16
A1 – A0
A2 – A15
18
9
9
UW
LW
WRITE
REGISTER
DATA–IN
REGISTERS
E
ENABLE
REGISTER
9
9
9
9
OUTPUT
BUFFER
G
DQ0 – DQ8
DQ9 – DQ17
NOTE:
All registers are positive–edge triggered. The ADSC or ADSP signals control the duration of the burst and the start of the
next burst. When ADSP is sampled low, any ongoing burst is interrupted and a read (independent of W and ADSC) is per-
formed using the new external address. Alternatively, an ADSP–initiated two cycle WRITE can be performed by asserting
ADSP and a valid address on the first cycle, then negating both ADSP and ADSC and asserting LW and/or UW with valid
data on the second cycle (see Single Write Cycle in WRITE CYCLES timing diagram).
When ADSC is sampled low (and ADSP is sampled high), any ongoing burst is interrupted and a read or write (dependent
on W) is performed using the new external address. Chip enable (E) is sampled only when a new base address is loaded.
After the first cycle of the burst, ADV controls subsequent burst cycles. When ADV is sampled low, the internal address
is advanced prior to the operation. When ADV is sampled high, the internal address is not advanced, thus inserting a wait
state into the burst sequence accesses. Upon completion of a burst, the address will wrap around to its initial state. See
BURST SEQUENCE TABLE.
Write refers to either or both byte write enables (LW, UW).
BURST SEQUENCE TABLE
(See Note)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A15 – A2
A15 – A2
A15 – A2
A15 – A2
A1
A1
A1
A1
A0
A0
A0
A0
NOTE: The burst wraps around to its initial state upon completion.
MOTOROLA FAST SRAM
MCM72BA32•MCM72BA64
5