HD66717
(Low-Power Dot-Matrix Liquid Crystal Display
Controller/Driver)
Description
The HD66717 dot-matrix liquid crystal display controller and driver LSI displays alphanumerics,
katakana, hiragana, and symbols. It can be configured to drive a dot-matrix liquid crystal display under
the control of an I
2
C bus, a clock-synchronized serial, or a 4- or 8-bit microprocessor. A single HD66717
is capable of displaying a maximum of four 12-character lines, 40 segments, and 10 annunciators. The
HD66717 incorporates all the functions required for driving a dot-matrix liquid crystal display such as
display RAM, character generator, and liquid crystal drivers, and a booster for LCD power supply.
The HD66717 provides various functions to reduce the power consumption of an LCD system such as
low-voltage operation of 2.4V or less, a booster for generating a maximum of triple LCD drive voltage
from the supplied voltage, and voltage-followers for decreasing the direct current flow in the LCD drive
bleeder-resistors. Combining these hardware functions with software functions such as standby and sleep
modes allows a fine power control. The HD66717, with the above functions, is suitable for any portable
battery-driven product requiring long-term driving capabilities and small size.
Features
•
5
×
8-dot matrix LCD drive
•
Four 12-character lines, 40 segments, and 10 annunciators
•
Low-power operation support:
2.4 to 5.5V (low voltage)
Double or triple booster for liquid crystal drive voltage
Electron volume function and voltage-followers for decreasing the direct current flow in the LCD
drive bleeder-resistors
Standby mode and sleep mode
Displays up to 10 static annunciators
2
•
I C bus or clock-synchronized serial interface; 4- or 8-bit parallel bus interface
•
60
×
8-bit display data RAM (60 characters max)
•
9,600-bit character generator ROM
240 characters (5
×
8 dots)
452
HD66717
•
32
×
5-bit character generator RAM
4 characters (5
×
8 dots)
•
8
×
5-bit segment RAM
40 segment-icons and marks max
•
60-segment
×
34-common liquid crystal display driver
•
Programmable display sizes and duty ratios (see List1)
•
Vertical smooth scroll
•
Double-height display
•
Wide range of instruction functions:
Display clear, display on/off, icon and mark control, character blink, white-black inverting
blinking cursor, icon and mark blink, cursor home, cursor on/off, white-black inverting raster-row
•
Hardware reset
•
Internal oscillation with an external resistor
•
Wide range of LCD drive voltages
3.0V to 13.0V
•
Slim chip with/without bump (for COB) and tape carrier package (TCP)
List 1
Programmable Display Sizes and Duty Ratios
Oscillation
Frequency
40 kHz
80 kHz
120 kHz
Current
Consumption
8 µA
15 µA
23 µA
Multi-plexed-Drive
Segments
40
40
40
Static-Drive
Annunciators
10
10
10
10
Display Size
1 line
×
12
characters
2 lines
×
12
characters
3 lines
×
12
characters
Duty Ratio
1/10
1/18
1/26
4 lines
×
12
1/34
160 kHz
30 µA
40
characters
Note: Current consumption excludes that for LCD power supply source; V
CC
= 3V.
List 2 Ordering Information
Type Name
HD66717A03TA0
HCD66717A03
HCD66717A03BP
HCD66717A13BP
External Dimensin
TCP
Bare chip
Au-bumped chip
Au-bumped chip
Up-side-down pattern of A03
Operation Voltage
2.4V to 5.5V
Internal Font
Japanese and European fonts
453
HD66717
LCD-II Family Comparison
Item
Power supply voltage
LCD-II
(HD44780U)
2.7V to 5.5V
HD66702R
5V ± 10% (standard)
2.7V to 5.5V
(low voltage)
3.0V to 8.3V
20 characters
×
2 lines
HD66710
2.7V to 5.5V
HD66712U
2.7V to 5.5V
Liquid crystal drive voltage 3.0 to 11.0V
Maximum display -
8 characters
×
2 lines
characters per chip
Segment display
Display duty ratio
CGROM
CGRAM
DDRAM
SEGRAM
Segment signals
Common signals
Liquid crystal drive
waveform
Clock source
Rf oscillation frequency
Liquid crystal voltage
booster circuit
Liquid crystal drive
operational amplifier
Bleeder-resistor for liquid
crystal drive
Liquid crystal contrast
adjuster
Key scan circuit
Extension driver control
signal
Reset function
Horizontal smooth scroll
Vertical smooth scroll
Number of displayed lines
Low power control
Bus interface
Package
None
1/8, 1/11, and
1/16
9,920 bits
(208 5-×-8 dot
characters and
32 5-×-10 dot
characters)
64 bytes
80 bytes
None
40
16
A
External resistor
or external clock
270 kHz ± 30%
None
None
External
None
None
Independent
control signal
Internal reset
circuit
Impossible
Impossible
1 or 2
None
4 or 8 bits
80-pin QFP1420
80-pin TQFP1414
80-pin bare chip
None
1/8, 1/11, and
1/16
7,200 bits
(160 5-×-7 dot
characters and
32 5-×-10 dot
characters)
64 bytes
80 bytes
None
100
16
B
External resistor
or external clock
320 kHz ± 30%
None
None
External
None
None
Independent
control signal
Internal reset
circuit
Impossible
Impossible
1 or 2
None
4 or 8 bits
144-pin FQFP2020
144-pin bare chip
3.0 to 13.0V
16 characters
×
2 lines/
8 characters
×
4 lines
40
1/17 and 1/33
9,600 bits
(240 5-×-8 dot
characters)
2.7 to 11.0V
24 characters
×
2 lines/
12 characters
×
4 lines
60 (extended to 80)
1/17 and 1/33
9,600 bits
(240 5-×-8 dot
characters)
64 bytes
80 bytes
8 bytes
40
33
B
External resistor
or external clock
270 kHz ± 30%
Double or triple
booster circuit
None
External
None
None
Used in common
with a driver
output pin
Internal reset
circuit
Dot unit
Impossible
1, 2, or 4
Low power mode
4 or 8 bits
100-pin QFP1420
100-pin TQFP1414
100-pin bare chip
64 bytes
80 bytes
16 bytes
60
34
B
External resistor
or external clock
270 kHz ± 30%
Double or triple
booster circuit
None
External
None
None
Independent
control signal
Internal reset
circuit or reset input
Dot unit and
line unit
Impossible
1, 2, or 4
Low power mode
Serial, 4, or 8 bits
128-pin TCP
128-pin bare chip
454
HD66717
LCD-II Family Comparison (cont)
Item
Power supply voltage
Liquid crystal drive voltage
Maximum display
characters per chip
HD66720
2.7V to 5.5V
3.0 to 11.0V
10 characters
×
1 line/
8 characters
×
2 lines
42 (extended to 80)
1/9 and 1/17
9,600 bits
(240 5-×-8 dot
characters)
64 bytes
40 bytes
16 bytes
42
17
B
External resistor
or external clock
160 kHz ± 30%
HD66717
2.4V to 5.5V
3.0 to 13.0V
12 characters
×
1 line/2 lines/3 lines/4 lines
HD66727
2.4V to 5.5V
3.0 to 13.0V
12 characters
×
1 line/2 lines/3 lines/4 lines
Segment display
Display duty ratio
CGROM
CGRAM
DDRAM
SEGRAM
Segment signals
Common signals
Liquid crystal drive
waveform
Clock source
Rf oscillation frequency
40 (and 10 annunciators)
1/10, 1/18, 1/26, and 1/34
9,600 bits
(240 5-×-8 dot
characters)
32 bytes
60 bytes
8 bytes
60
34
B
External resistor
or external clock
1-line mode: 40 kHz ± 30%
2-line mode: 80 kHz ± 30%
3-line mode: 120 kHz ± 30%
4-line mode: 160 kHz ± 30%
Double or triple
booster circuit
Built-in for each V1 to V5
Internal 1/4 and 1/6 bias
resistors
Incorporated
40 (and 12 annunciators)
1/10, 1/18, 1/26, and 1/34
11,520 bits
(240 6-×-8 dot
characters)
32 bytes
60 bytes
8 bytes
60
34
B
External resistor
or external clock
1-line mode: 40 kHz ± 30%
2-line mode: 80 kHz ± 30%
3-line mode: 120 kHz ± 30%
4-line mode: 160 kHz ± 30%
Double or triple
booster circuit
Built-in for each V1 to V5
Internal 1/4 and 1/6 bias
resistors
Incorporated
4
×
8 = 32 keys
None
Reset input
Impossible
Dot (raster-row) unit
1, 2, 3, or 4
Standby mode and
sleep mode
2
I C or clock-synchronized serial
Slim chip with/without bumps
TCP
Liquid crystal voltage
booster circuit
Liquid crystal drive
operational amplifier
Bleeder-resistor for liquid
crystal drive
Liquid crystal contrast
adjuster
Key scan circuit
Extension driver control
signal
Reset function
Double or triple
booster circuit
None
External
None
5
×
6 = 30 keys
None
Independent
None
control signal
Internal reset
Reset input
circuit or reset input
Horizontal smooth scroll
Dot unit and
Impossible
line unit
Vertical smooth scroll
Impossible
Dot (raster-row) unit
Number of displayed lines 1 or 2
1, 2, 3, or 4
Low power control
Low power mode and sleep Standby mode and
mode
sleep mode
2
Bus interface
Serial
I C, serial, 4, or 8 bits
Package
100-pin QFP1420
Slim chip with/without bumps
100-pin TQFP1414
TCP
100-pin bare chip
455
HD66717
HD66717 Block Diagram
OSC1
OSC2
SFT
EXM
AGND
CPG
RESET*
TEST
Instruction
register
(IR)
Instruction
decoder
Timing generator
ASEG1–
ASEG10
Annunciator
driver
7
ACOM
COM1–
COM32
8
IM1/0
Address
counter
7
RS/CS*
E/SCL
RW/SDA
System
interface
• I
2
C bus
• Clock-
synchro-
nized
serial
• 4 bits
• 8 bits
Display data RAM
(DDRAM)
60
×
8 bits
34-bit Common
signal
shift
driver
register
COMS1/2
7
8
SEG1–
Segment
SEG60
signal
driver
DB7–DB6
Input/
output
buffer
8
Data
register
(DR)
5
Busy
flag
3
7
5
8
60-bit
shift
register
60-bit
latch
circuit
DB5/ID5
–DB0/ID0
8
Segment
RAM
(SEGRAM)
8 bytes
Vci
C1
C2
V5OUT2
V5OUT3
Booster
Character
generator
RAM
(CGRAM )
32 bytes
Character
generator
ROM
(CGROM)
9,600 bits
Cursor and
blink
controller
LCD drive
voltage
selector
5
5
Parallel/serial converter
V
CC
GND
+–
R
R
+–
2R
+–
R
+–
R
+ –
VR
OPOFF
V1OUT
V2
V2OUT
V3
V3OUT
V4OUT
V5OUT
V
EE
456
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