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MCM6206DP20

Description
32K x 8 Bit Fast Static RAM
Categorystorage    storage   
File Size83KB,8 Pages
ManufacturerMotorola ( NXP )
Websitehttps://www.nxp.com
Download Datasheet Parametric View All

MCM6206DP20 Overview

32K x 8 Bit Fast Static RAM

MCM6206DP20 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerMotorola ( NXP )
package instruction0.300 INCH, PLASTIC, DIP-28
Reach Compliance Codeunknow
ECCN codeEAR99
Maximum access time20 ns
JESD-30 codeR-PDIP-T28
JESD-609 codee0
length34.67 mm
memory density262144 bi
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of ports1
Number of terminals28
word count32768 words
character code32000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32KX8
Output characteristics3-STATE
ExportableYES
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum seat height4.57 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
width7.62 mm
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM6206D/D
32K x 8 Bit Fast Static RAM
The MCM6206D is fabricated using Motorola’s high–performance silicon–gate
CMOS technology. Static design eliminates the need for external clocks or timing
strobes, while CMOS circuitry reduces power consumption and provides for
greater reliability.
This device meets JEDEC standards for functionality and pinout, and is avail-
able in plastic dual–in–line and plastic small–outline J–leaded packages.
Single 5 V
±
10% Power Supply
Fully Static — No Clock or Timing Strobes Necessary
Fast Access Times: 12, 15, 20, and 25 ns
Equal Address and Chip Enable Access Times
Output Enable (G) Feature for Increased System Flexibility and to
Eliminate Bus Contention Problems
Low Power Operation: 125 – 140 mA Maximum AC
Fully TTL Compatible — Three State Output
MCM6206D
P PACKAGE
300 MIL PLASTIC
CASE 710B–01
J PACKAGE
300 MIL SOJ
CASE 810B–03
PIN ASSIGNMENT
BLOCK DIAGRAM
A1
A3
A4
A6
A7
A8
A9
A11
ROW
DECODER
MEMORY MATRIX
256 ROWS x
128 x 8 COLUMNS
VCC
VSS
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
DQ0
DQ7
INPUT
DATA
CONTROL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V CC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
.
.
.
VSS
COLUMN I/O
COLUMN DECODER
PIN NAMES
A0 – A14 . . . . . . . . . . . . . Address Input
DQ0 – DQ7 . . . Data Input/Data Output
W . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . Output Enable
E . . . . . . . . . . . . . . . . . . . . . . Chip Enable
VCC . . . . . . . . . . . Power Supply (+ 5 V)
VSS . . . . . . . . . . . . . . . . . . . . . . . Ground
E
W
G
A0
A2
A5
A10 A12 A13 A14
REV 1
5/95
©
Motorola, Inc. 1994
MOTOROLA FAST SRAM
MCM6206D
1
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