HD74HC194
4-bit Bidirectional Universal Shift Register
Description
This bidirectional shift register is designed to incorporate virtually all of the features a system designer may
want in a shift register. It features parallel inputs, parallel outputs, right shift and left shift serial inputs,
operating mode control inputs, and a direct overriding clear line. The register has four distinct modes of
operation: parallel (broadside) load, shift right (in the direction Q
A
toware Q
D
); shift left; inhibit clock (do
nothing).
Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode
control inputs, S
0
and S
1
, high. The data are loaded into their respective flip-flops and appear at the outputs
after the positive transition of the clock input. During loading, serial data flow is inhibited. Shift right is
accomplished synchronously with the rising edge of the clock pulse when S
0
is high and S
1
is low. Serial
data for this mode is entered at the shift right data input. When S
0
is low and S
1
is high, data shifts left
synchronously and new data is entered at the shift left serial input. Clocking of the flip-flops is inhibited
when both mode control inputs are low. The mode control inputs should be changed only when the clock
input is high.
Features
•
•
•
•
•
High Speed Operation: t
pd
(Clock to Q) = 12 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: V
CC
= 2 to 6 V
Low Input Current: 1 µA max
Low Quiescent Supply Current: I
CC
(static) = 4 µA max
HD74HC194
Function Table
Inputs
Operating
Mode
Clear
Parallel load
Shift right
Mode
Clear S
1
L
H
H
H
Shift left
H
H
Hold
H
H
H
H :
L :
X :
X
H
L
L
H
H
L
X
X
S
0
X
H
H
H
L
L
L
X
X
X
L
H
Clock
X
Serial
Shift Left
X
X
X
X
H
L
X
X
X
Shift Right
X
X
H
L
X
X
X
X
X
Parallel
Outputs
Q
B
L
b
Q
An
Q
An
Q
Cn
Q
Cn
Q
B0
Q
B0
Q
B0
Q
C
L
c
Q
Bn
Q
Bn
Q
Dn
Q
Dn
Q
C0
Q
C0
Q
C0
Q
D
L
d
Q
Cn
Q
Cn
H
L
Q
D0
Q
D0
Q
D0
A B C D Q
A
X X
a
b
X X L
c
d
a
X X
X X
X X
X X
X X
X X
X X
X X H
X X L
X X Q
Bn
X X Q
Bn
X X Q
A0
X X Q
A0
X X Q
A0
high level (Steady state)
low level (Steady state)
don’t care
:
transition from low to high level.
a, b, c, d : the level of steady-state input at inputs A, B, C or D respectively.
Q
A0
, Q
B0
, Q
C0
, Q
D0
: the level of Q
A
, Q
B
, Q
C
or Q
D
respectively, before the indicated steady-state input
conditions were established.
Q
An
, Q
Bn
, Q
Cn
, Q
Dn
the clock.
:
the level of Q
A
, Q
B
, Q
C
or Q
D
respectively before the most recent
transition of
2
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