DSC2011
Low-Jitter Configurable Dual CMOS Oscillator
General Description
The DSC2011 series of high performance
dual output CMOS oscillators utilize a proven
silicon MEMS technology to provide excellent
jitter and stability while incorporating
additional device functionality.
The two
CMOS outputs are controlled by separate
supply voltages to allow for independent
voltage level control. The frequencies of the
outputs can be identical or independently
derived from a common PLL frequency
source. The DSC2011 has provision for up to
eight user-defined pre-programmed, pin-
selectable output frequency combinations.
The DSC2011 is also equipped with
independent pin-selectable output drive
strengths for each output to reduce EMI and
noise.
DSC2011 is packaged in a 14-pin 3.2x2.5
mm
QFN
package
and
available
in
temperature grades from Ext. Commercial to
Automotive.
Features
Low RMS Phase Jitter: <1 ps (typ)
High Stability: ±10, ±25, ±50 ppm
Wide Temperature Range
o
Automotive: -55° to 125° C
o
Ext. Industrial: -40° to 105° C
o
Industrial: -40° to 85° C
o
Ext. commercial: -20° to 70° C
High Supply Noise Rejection: -50 dBc
Two Independent CMOS Outputs
Pin-Selectable Configurations
o
2-bit Output Drive Strength
o
3-bit Output Frequency Combinations
Short Lead Times: 2 Weeks
Wide Freq. Range:
o
CMOS Output: 2.3 to 170 MHz
Miniature Footprint of 3.2x2.5mm
Excellent Shock & Vibration Immunity
o
Qualified to MIL-STD-883
High Reliability
o
20x better MTF than quartz oscillators
Supply Range of 2.25 to 3.6 V
Lead Free & RoHS Compliant
Block Diagram
Applications
Consumer Electronics
Storage Area Networks
o
SATA, SAS, Fibre Channel
Passive Optical Networks
o
EPON, 10G-EPON, GPON, 10G-PON
Ethernet
o
1G, 10GBASE-T/KR/LR/SR, and FCoE
HD/SD/SDI Video & Surveillance
PCI Express
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DSC2011
Page 1
MK-Q-B-P-D-12042602-2
DSC2011
Low-Jitter Configurable Dual CMOS Oscillator
Pin Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin Name
Enable
NC
O2S0
GND
FS0
FS1
FS2
Output1
O1S0
O1S1
Output2
VDD2
VDD
O2S1
Pin Type
I
NA
I
Power
I
I
I
O
I
I
O
Power
Power
I
Description
Enables outputs when high and disables when low
Leave unconnected or grounded
Least significant bit for drive strength selection for Output 2
Ground
Least significant bit for frequency selection
Middle bit for frequency selection
Most significant bit for frequency selection
CMOS output 1
Least significant bit for drive strength selection for output 1
Most significant bit for drive strength selection for output 1
CMOS output 2
Power Supply for Output 2
Power Supply
Most significant bit for drive strength selection for output 2
Operational Description
The DSC2011 is a dual output CMOS oscillator
consisting of a MEMS resonator and a support
PLL IC. The two CMOS outputs are generated
through independent 8-bit programmable
dividers from the output of the internal PLL.
For temp ranges up to Industrial, two
constraints are imposed on the output
frequencies: 1) f
2
=M x f
1
/N, where M and N
are even integers between 4 and 254, 2)
1.2GHz < N x f
2
< 1.7GHz. Please consult
factory for acceptable frequency combinations
for other temp ranges.
The actual frequencies output by the DSC2011
are controlled by an internal pre-programmed
memory (OTP).
This memory stores all
coefficients required by the PLL for up to eight
different frequency combinations.
Three
control pins (FS0 – FS2) select the output
frequency combination.
Discera supports
customer defined versions of the DSC2011.
Standard frequency options are described in in
the following sections.
The DSC2011 has independent control of the
output voltage levels of the two outputs. The
high voltage level of Output 1 is equal to the
main supply voltage, VDD (pin 13). VDD2
(pin 12) sets the high voltage level of Output
2. VDD2 must be equal to or less than VDD at
all times to insure proper operation. VDD2
can be as low as 1.65V.
When Enable (pin 1) is floated or connected to
VDD, the DSC2011 is in operational mode.
Driving Enable to ground will tri-state both
output drivers (hi-impedance mode).
The DSC2011 has programmable output drive
strength for each output. Using two control
pins (OXS0-OXS1) for each output, the drive
strength can be independently adjusted to
match circuit board impedances to reduce
power supply noise, overshoot/undershoot
and EMI. Table 1 displays typical rise / fall
times for the output with a 15pf load
capacitance as a function of these control pins
at VDD=3.3V and room temperature.
Table 1. Rise/Fall times for drive strengths
Output Drive Strength Bits
[OXS1, OXS0] -
Default [11]
00
t
r
(ns)
t
f
(ns)
1.6
2.4
01
1.4
2.2
10
1.2
1.5
11
1.1
1.4
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DSC2011
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MK-Q-B-P-D-12042602-2
DSC2011
Low-Jitter Configurable Dual CMOS Oscillator
Output Clock Frequencies
Table 2 lists the standard frequency configurations and the associated ordering information to be
used in conjunction with the ordering code above. Customer defined combinations are available.
Table 2. Pre-programmed pin-selectable output frequency combinations
Ordering
Info
E0001
E0002
E0004
E0005
E0006
E0007
E0008
Freq
(MHz)
f
OUT1
f
OUT2
f
OUT1
f
OUT2
f
OUT1
f
OUT2
f
OUT1
f
OUT2
f
OUT1
f
OUT2
f
OUT1
f
OUT2
f
OUT1
f
OUT2
EXXXX
f
OUT1
f
OUT2
Freq Select Bits [FS2, FS1, FS0] –
Default is [111]
000
27
24
106.25
25
24
24
25
25
27
13.5
24
40
40
200
001
25
125
100
100
75
75
0*
0*
74.175
37.0875
0*
0*
40
128
010
50
125
125
50
125
125
0*
0*
74.25
37.125
0*
0*
40
120
011
54
27
100
50
48
48
0*
0*
148.35
74.175
0*
0*
20
120
100
48
24
156.25
25
74.25
74.25
0*
0*
148.5
74.25
0*
0*
40
100
101
24
50
156.25
125
148.5
148.5
0*
0*
0*
0*
0*
0*
20
100
110
24
54
125
25
50
50
0*
0*
0*
0*
0*
0*
40
80
111
24
27
156.25
156.25
25
25
25
25
0*
0*
0*
0*
20
80
Contact factory for additional configurations.
Frequency select bit are weakly tied high so if left unconnected the default setting will be [111] and
the device will output the associated frequency highlighted in
Bold.
0* – denotes invalid selection, output frequency is not specified.
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DSC2011
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MK-Q-B-P-D-12042602-2
DSC2011
Low-Jitter Configurable Dual CMOS Oscillator
Absolute Maximum Ratings
Item
Supply Voltage
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
ESD
HBM
MM
CDM
Ordering Code
Condition
Temp Range
E: -20 to 70
I: -40 to 85
L: -40 to 105
M: -55 to 125
Packing
T: Tape & Reel
: Tube
Min
-0.3
-0.3
-
-55
-
-
Max
+4.0
V
DD
+0.3
+150
+150
+260
4000
400
1500
Unit
V
V
°C
°C
°C
V
40sec max.
DSC2011
F I 2
-
xxxxx
T
Freq (MHz)
See Freq. table
Package
F: 3.2x2.5mm
Stability
1: ±50ppm
2: ±25ppm
5: ±10ppm
Note: 1000+ years of data retention on internal memory
Specifications
Parameter
Supply Voltage
Supply Current
1
(Unless specified otherwise: T=25° C, max CMOS drive strength)
Condition
V
DD
I
DD
I
DD
Δf
Δf
t
SU
V
IH
V
IL
t
DA
t
EN
Pull-up exists on all digital IO
EN pin low – outputs are disabled
EN pin high – outputs are enabled
C
L
=15pF, F
O1
=F
O2
=125 MHz
Includes frequency variations due
to initial tolerance, temp. and
power supply voltage
1 year @25°C
T=25°C
0.75xV
DD
-
Min.
2.25
Typ.
21
32
Max.
3.6
23
Unit
V
mA
mA
Supply Current
2
Frequency Stability
Aging
Startup Time
3
Input Logic Levels
Input logic high
Input logic low
Output Disable Time
4
Output Enable Time
Pull-Up Resistor
2
±10
±25
±50
±5
5
-
0.25xV
DD
5
20
40
ppm
ppm
ms
V
ns
ns
kΩ
CMOS Outputs
Output Logic Levels
Output logic high
Output logic low
Output Transition time
4
Rise Time
Fall Time
Frequency
Output Duty Cycle
Period Jitter
5
Integrated Phase Noise
Notes:
1.
2.
3.
4.
5.
V
OH
V
OL
t
R
t
F
f
0
SYM
J
PER
J
CC
I=±6mA
20% to 80%
C
L
=15pf
Commercial/Industrial temp range
Automotive temp range
F
O1
=F
O2
=125 MHz
200kHz to 20MHz @ 125MHz
100kHz to 20MHz @ 125MHz
12kHz to 20MHz @ 125MHz
0.9xV
DD
-
1.1
1.4
2.3
45
3
0.3
0.38
1.7
-
0.1xV
DD
2
2
170
100
55
V
ns
MHz
%
ps
RMS
ps
RMS
2
Pin 4 V
DD
should be filtered with 0.01uf capacitor.
Output is enabled if Enable pad is floated or not connected.
t
su
is time to 100PPM stable output frequency after V
DD
is applied and outputs are enabled.
Output Waveform and Test Circuit figures below define the parameters.
Period Jitter includes crosstalk from adjacent output.
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DSC2011
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MK-Q-B-P-D-12042602-2
DSC2011
Low-Jitter Configurable Dual CMOS Oscillator
Nominal Performance Parameters
(Unless specified otherwise: T=25° C, V
DD
=3.3 V)
2.5
25MHz-CMOS
Phase Jitter (ps RMS)
2.0
50MHz-CMOS
106MHz-CMOS
125MHz-CMOS
1.5
1.0
0.5
0.0
0
200
400
600
800
1000
Low-end of integration BW: x kHz to 20 MHz
CMOS Phase jitter (integrated phase noise)
Output Waveform: CMOS
t
R
V
OH
t
F
Output
V
OL
1/f
o
t
DA
V
IH
t
EN
Enable
V
IL
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DSC2011
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MK-Q-B-P-D-12042602-2
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