EtronTech
Features
•
Fast Access Time: 30/35/40/45ns
•
Fast EDO Page Cycle Time: 13.3/15/16/18ns
•
EDO Page Mode Operation
•
Single +5V
¡Ó
10% Power Supply
•
Low Power Dissipation
•
Individual Byte Control via Dual CAS Inputs
•
Three Refresh Modes
•
512-Cycle Refresh in 8ms(9 rows and 9 columns)
•
TTL Compatible
•
40-Pin, 400-mil Plastic SOJ Package, or
40/44-Pin, 400-mil Plastic TSOP-II Package.
Em614163A-30/35/40/45
256K x 16 High Speed EDO DRAM
Preliminary
Pin Assignment (Top View)
40-Pin SOJ
Vcc
I/O0
I/O1
I/O2
I/O3
Vcc
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
A0
A1
A2
A3
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Vss
I/O15
I/O14
I/O13
I/O12
Vss
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
Vss
40/44-Pin TSOP-II
Vcc
I/O0
I/O1
I/O2
I/O3
Vcc
I/O4
I/O5
I/O6
I/O7
1
2
3
4
5
6
7
8
9
10
44
43
42
41
40
39
38
37
36
35
Vss
I/O15
I/O14
I/O13
I/O12
Vss
I/O11
I/O10
I/O9
I/O8
Ordering Information
Part Number
Em614163A-30
EM614163TS-30
Em614163A-35
EM614163TS-35
Em614163A-40
EM614163TS-40
Em614163A-45
EM614163TS-45
Speed
30ns
30ns
35ns
35ns
40ns
40ns
45ns
45ns
Package
SOJ
TSOP-II
SOJ
TSOP-II
SOJ
TSOP-II
SOJ
TSOP-II
NC
NC
WE
RAS
NC
A0
A1
A2
A3
Vcc
13
14
15
16
17
18
19
20
21
22
32
31
30
29
28
27
26
25
24
23
NC
LC AS
UCAS
OE
A8
A7
A6
A5
A4
Vss
Pin Names
A0 - A8
RAS
UCAS
LCAS
WE
OE
Address Inputs
Row Address Strobe
Column Address Strobe
(Upper Byte Control)
Column Address Strobe
(Lower Byte Control)
Write Enable
Output Enable
Data Input/Output
+5V Power Supply
Ground
No Connection
Key Specifications
Speed
-30
-35
-40
-45
t
RAC
30ns
35ns
40ns
45ns
t
CAC
9ns
10ns
11ns
12ns
t
AA
16ns
18ns
20ns
22ns
t
OEA
9ns
9ns
10ns
10ns
t
RC
t
PC
53ns 13.3ns
60ns 15ns
66ns 16ns
75ns 18ns
I/O0 - I/O15
V
CC
V
SS
NC
Overview
The Em614163A-30/35/40/45 is a high speed
EDO(Extended Data Output) DRAM organized in
262,144 words by 16 bits. It supports EDO Page
Mode and 16-bit data width for high data bandwidth
applications. The EDO Page Mode is an
accelerated access that provides a shorter page
cycle and a faster data access time than the
traditional Fast Page Mode.
Compared with Fast Page Mode DRAM, the
EDO DRAM data output will be held valid after
CAS
goes HIGH, as long as
RAS
and
OE
are held LOW
and
WE
is held HIGH. This feature allows
CAS
precharge time to occur without the output data
going invalid. Therefore, the EDO
CAS
timing can be
condensed to carry more data out in a given period.
The Em614163A-30/35/40/45 fully utilizes the
EDO Page Mode advantages. It allows 512 random
access within a page with a fast cycle time as short
as 13.3/15/16/18 ns.
The Em614163A-30/35/40/45 is ideally suitable
for high performance graphics frame buffers, CD-
ROMs, disk drivers, set top boxes, and DSP
applications.
Etron Technology, Inc.
1F, No. 1, Prosperity Rd. 1, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C.
TEL: (886)-3-5782345 FAX: (886)-3-5779001
Etro n Techn olo gy, Inc. reserves th e right to make chan ges to its pro ducts and specificat ion s
without notice.
April 1997
EtronTech
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to V
SS
Supply voltage relative to V
SS
Short circuit output current
Power dissipation
Operating temperature
Storage temperature
Symbol
V
T
V
CC
I
OUT
P
T
T
OPT
T
STG
Value
Em614163A-30/35/40/45
Unit
V
V
mA
W
°C
°C
- 0.5 to +7.0
- 0.5 to +7.0
50
1.0
0 to +70
- 55 to +125
Capacitance
(Ta = 25°C; V
CC
= 5V
¡Ó
10%; f = 1MHz)
Parameter
Input capacitance (A0 - A8)
Input capacitance ( RAS , UCAS , LCAS , WE , OE )
Output capacitance(I/O0 - I/O15)
Notes:
1. Capacitance is sampled and not 100% tested.
Symbol Typ. Max. Unit
C
I
1
C
I
2
C
I/O
¡Ð
¡Ð
¡Ð
5
5
7
pF
pF
pF
Note
1
1
1
Truth Table
Function
Standby
Read: Word
Read: Lower Byte
Read: Upper Byte
Write: Word
(Early Write)
Write: Lower Byte
(Early)
Write: Upper Byte
(Early)
Read Write
EDO-Page-
Mode Read
EDO-Page-
Mode Write
EDO-
Page-Mode
Read-Write
Hidden
Refresh
CBR Refresh
1st Cycle
2nd Cycle
1st Cycle
2nd Cycle
1st Cycle
2nd Cycle
Read
Write
RAS
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
→
H
→
L
L
→
H
→
L
L
H
→
L
LCAS UCAS
H
→
X
L
L
H
L
L
H
L
H
→
L
H
→
L
H
→
L
H
→
L
H
→
L
H
→
L
L
L
H
L
H
→
X
L
H
L
L
H
L
L
H
→
L
H
→
L
H
→
L
H
→
L
H
→
L
H
→
L
L
L
H
L
WE
X
H
H
H
L
L
L
H
→
L
H
H
L
L
H
→
L
H
→
L
H
L
X
X
OE
X
L
L
L
X
X
X
L
→
H
L
L
X
X
L
→
H
L
→
H
L
X
X
X
Addresses
t
R
t
C
X
ROW
ROW
ROW
ROW
ROW
ROW
ROW
ROW
n/a
ROW
n/a
ROW
n/a
ROW
ROW
ROW
X
X
COL
COL
COL
COL
COL
COL
COL
COL
COL
COL
COL
COL
COL
COL
COL
n/a
X
High-Z
DQs
Data-out
Lower byte, data-out
Upper byte, high-Z
Lower byte, high-Z
Upper byte, data-out
Data-in
Lower byte, data-in
Upper byte, high-Z
Lower byte, high-Z
Upper byte, data-in
Data-out, Data-in
Data-out
Data-out
Data-in
Data-in
Data-out, Data-in
Data-out, Data-in
Data-out
Data-in
High-Z
High-Z
Notes
1, 2
2
2
1
1
1, 2
1, 2
2
1, 3
4
RAS# only refresh
Notes:
1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).
2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).
3. EARLY WRITE only.
Preliminary
3
April 1997
EtronTech
Recommended Operating Conditions
Parameter
Supply voltage
Input high voltage
Input low voltage
Notes:
Symbol
V
SS
V
CC
V
IH
V
IL
Min
0
4.5
2.4
- 0.5
Typ
0
5.0
¡Ð
¡Ð
Em614163A-30/35/40/45
Max
0
5.5
V
CC
+ 0.3
0.8
Unit
V
V
V
V
Notes
2
1, 2
1
1, 3
1. All voltage referenced to V
SS
.
2. The supply voltage with all V
CC
pins must be the same level.
The supply voltage with all V
SS
pins must be the same level.
3. V
IL
(min.) = - 1.2V for pulse width
¡Ø
30ns.
DC Characteristics
T
A
= 0 to +70°C; Vcc = +5V
±
10%, Vss = 0V
Em614163A
Parameter
Symbol
Test Conditions
Min
Operating current
I
CC
1
RAS
cycling
LCAS
,
UCAS
cycling
¡Ð
-30/35/40/45
Max
280/250/225/200
Unit
Notes
mA
1, 2
Standby current
I
CC
2
RAS
-only refresh
I
CC
3
current
Standby current
CAS
-before-
RAS
t
RC
= min.
RAS
,
LCAS
,
UCAS
= V
IH
Dout = High-Z
RAS
,
LCAS
,
UCAS
,
OE
=
V
CC
- 0.2V
Dout = High-Z
RAS
cycling,
CAS
= V
IH
t
RC
= min.
RAS = V
IH
LCAS
,
UCAS
= V
IL
Dout = enable
t
RC
= min.
RAS
,
CAS
cycling
t
PC
= min.
0V
¡Õ
Vin
¡Õ
V
CC
0V
¡Õ
Vout
¡Õ
V
CC
Dout = Disable
I
OH
= - 2.5 mA
I
OL
= + 2.1 mA
¡Ð
¡Ð
¡Ð
2
1
280/250/225/200
5
mA
mA
mA
mA
2
1
I
CC
5
I
CC
6
I
CC
7
I
LI
I
LO
V
OH
V
OL
¡Ð
refresh current
Fast page mode
current
Input leakage
current
Output leakage
current
Output high voltage
Output low voltage
Notes:
¡Ð
¡Ð
280/250/225/200
280/250/225/200
10
10
mA
mA
µA
µA
V
1, 3
-10
-10
2.4
0.4
V
1. I
CC
depends on output load condition when the device is selected. I
CC
-max is specified at the output open
condition.
2. Address can be changed once or less while RAS = V
IL
.
3. Address can be changed once or less while LCAS and UCAS = V
IL
.
4. All the V
CC
pins shall be supplied with the same voltage. And all the V
SS
pins shall be supplied with the
same voltage.
Preliminary
5
April 1997
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