IC61LV6416
Document Title
64K x 16 Hight Speed SRAM with 3.3V
Revision History
Revision No
0A
1
Draft Date
Remark
September 12,2001
History
Initial Draft
2
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The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
AHSR026-0A
09/12/2001
1
IC61LV6416
64K x 16 HIGH-SPEED CMOS STATIC RAM
WITH 3.3V SUPPLY
FEATURES
• High-speed access time: 8, 10, 12, and 15 ns
• CMOS low power operation
— 250 mW (typical) operating
— 250 µW (typical) standby
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
DESCRIPTION
The
ICSI
IC61LV6416 is a high-speed, 1,048,576-bit static
RAM organized as 65,536 words by 16 bits. It is fabricated
using
ICSI
's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design
techniques, yields access times as fast as 8 ns with low power
consumption.
When
CE
is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip Enable and
Output Enable inputs,
CE
and
OE.
The active LOW Write
Enable (WE) controls both writing and reading of the memory.
A data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
The IC61LV6416 is packaged in the JEDEC standard 44-pin
400mil SOJ, 44-pin 400mil TSOP-2, and 48-pin 6*8mm TF-
BGA.
FUNCTIONAL BLOCK DIAGRAM
A0-A15
DECODER
64K x 16
MEMORY ARRAY
VCC
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
COLUMN I/O
CE
OE
WE
UB
LB
CONTROL
CIRCUIT
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
AHSR026-0A
09/12/2001
IC61LV6416
PIN CONFIGURATIONS
44-Pin SOJ
A15
A14
A13
A12
A11
CE
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A10
A9
A8
A7
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A0
A1
A2
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A3
A4
A5
A6
NC
44-Pin TSOP-2
A15
A14
A13
A12
A11
CE
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A10
A9
A8
A7
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A0
A1
A2
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A3
A4
A5
A6
NC
1
2
3
4
5
6
7
8
9
48-Pin 6x8mm TF-BGA
1
A
B
C
D
E
F
G
H
LB
I/O
0
I/O
1
GND
Vcc
I/O
5
I/O
7
NC
PIN DESCRIPTIONS
5
A6
CE
I/O
13
I/O
12
I/O
11
I/O
10
WE
A15
2
OE
UB
I/O
2
I/O
3
I/O
4
I/O
6
NC
A12
3
A3
A2
A0
NC
NC
A9
A11
A13
4
A7
A1
A4
A5
NC
A8
A10
A14
6
N/C
I/O
15
I/O
14
Vcc
GND
I/O
9
I/O
8
NC
A0-A15
I/O0-I/O15
CE
OE
WE
LB
UB
NC
Vcc
GND
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
Lower-byte Control (I/O0-I/O7)
Upper-byte Control (I/O8-I/O15)
No Connection
Power
Ground
TRUTH TABLE
Mode
Not Selected
Output Disabled
Read
WE
X
H
X
H
H
H
L
L
L
CE
H
L
L
L
L
L
L
L
L
OE
X
H
X
L
L
L
X
X
X
LB
X
X
H
L
H
L
L
H
L
UB
X
X
H
H
L
L
H
L
L
I/O PIN
I/O0-I/O7 I/O8-I/O15
High-Z
High-Z
High-Z
D
OUT
High-Z
D
OUT
D
IN
High-Z
D
IN
High-Z
High-Z
High-Z
High-Z
D
OUT
D
OUT
High-Z
D
IN
D
IN
Vcc Current
I
SB
1
, I
SB
2
I
CC
I
CC
10
11
12
Write
I
CC
Integrated Circuit Solution Inc.
AHSR026-0A
09/12/2001
3
IC61LV6416
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
STG
P
T
I
OUT
Parameter
Terminal Voltage with Respect to GND
Storage Temperature
Power Dissipation
DC Output Current (LOW)
Value
–0.5 to Vcc+0.5
–65 to +150
1.5
20
Unit
V
°C
W
mA
Note:
1. Stress greater than those listed under
ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the
device. This is a stress rating only and
functional operation of the device at
these or any other conditions above
those indicated in the operational sec-
tions of this specification is not implied.
Exposure to absolute maximum rating
conditions for extended periods may
affect reliability.
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
Vcc
3.3V ± 10%
3.3V ± 10%
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
(1)
Input Leakage
Output Leakage
GND
≤
V
IN
≤
V
CC
GND
≤
V
OUT
≤
V
CC
, Outputs Disabled
Com.
Ind.
Com.
Ind.
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
Min.
2.4
—
2
–0.3
–2
-5
–2
-5
Max.
—
0.4
V
CC
+ 0.3
0.8
2
5
2
5
Unit
V
V
V
V
µA
µA
Notes:
1. V
IL
(min.) = –2.0V for pulse width less than 10 ns.
2. The Vcc operating range for 8 ns is 3.3V +10%, -5%.
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
Symbol
I
CC
I
SB
1
Parameter
Vcc Dynamic Operating
Supply Current
TTL Standby Current
(TTL Inputs)
CMOS Standby
Current (CMOS Inputs)
Test Conditions
V
CC
= Max.,
I
OUT
= 0 mA, f = f
MAX
V
CC
= Max.,
V
IN
= V
IH
or V
IL
CE
≥
V
IH
, f = 0
V
CC
= Max.,
CE
≥
V
CC
– 0.2V,
V
IN
≥
V
CC
– 0.2V, or
V
IN
≤
0.2V, f = 0
Com.
Ind.
Com.
Ind.
Com.
Ind.
-8 ns
Min. Max.
—
—
—
—
—
—
220
230
30
40
10
15
-10 ns
Min. Max.
—
—
—
—
—
—
200
210
30
40
10
15
-12 ns
Min. Max.
—
—
—
—
—
—
180
190
30
40
10
15
-15 ns
Min. Max.
—
—
—
—
—
—
180
190
30
40
10
15
Unit
mA
mA
I
SB
2
mA
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
4
Integrated Circuit Solution Inc.
AHSR026-0A
09/12/2001
IC61LV6416
CAPACITANCE
(1)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
6
8
Unit
pF
pF
1
2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
15
—
15
7
6
—
6
—
7
6
—
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-8
Symbol
Parameter
Read Cycle Time
Address Access Time
Output Hold Time
CE
Access Time
OE
Access Time
Min.
8
—
3
—
—
0
0
0
3
—
0
0
Max.
—
8
—
8
4
4
—
4
—
4
4
—
-10
Min. Max.
10
—
3
—
—
—
0
0
3
—
0
0
—
10
—
10
5
5
—
5
—
5
5
—
-12
Min. Max.
12
—
3
—
—
—
0
0
3
—
0
0
—
12
—
12
6
6
—
6
—
6
6
—
-15
Min. Max.
15
—
3
—
—
0
0
0
3
—
0
0
t
RC
t
AA
t
OHA
t
ACE
t
DOE
3
4
5
6
7
8
9
t
HZOE
(2)
OE
to High-Z Output
t
LZOE
(2)
OE
to Low-Z Output
t
HZCE
(2
t
BA
t
HZB
t
LZB
CE
to High-Z Output
LB, UB
Access Time
LB, UB
to High-Z Output
LB, UB
to Low-Z Output
t
LZCE
(2)
CE
to Low-Z Output
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of
0 to 3.0V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1a and 1b
10
319
Ω
3.3V
Notes:
1. The Vcc operating range for 8 ns is 3.3V +10%, -5%.
AC TEST LOADS
319
Ω
3.3V
11
353
Ω
OUTPUT
30 pF
Including
jig and
scope
353
Ω
OUTPUT
5 pF
Including
jig and
scope
12
Figure 1a.
Integrated Circuit Solution Inc.
AHSR026-0A
09/12/2001
Figure 1b.
5
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