K7N403609B
K7N401809B
Document Title
128Kx36 & 256Kx18 Pipelined NtRAM
TM
128Kx36 & 256Kx18-Bit Pipelined NtRAM
TM
Revision History
Rev. No.
0.0
0.1
History
1. Initial document.
1. Changed DC parameters
Icc ; from 470mA to 400mA at -25,
from 440mA to 360mA at -22,
from 400mA to 330mA at -20,
from 370mA to 310mA at -18,
I
SB
; from 180mA
from 170mA
from 160mA
from 150mA
I
SB1
; from 100mA
0.2
1.0
to
to
to
to
to
160mA at -25,
155mA at -22,
150mA at -20,
140mA at -18,
80mA
Aug. 11. 2001
Nov. 15. 2001
Preliminary
Final
Draft Date
May. 15. 2001
June. 12. 2001
Remark
Preliminary
Preliminary
1. Add x32 org. and industrial temperature
1. Final spec release
2. Changed Pin Capacitance
- Cin ; from 5pF to 4pF
- Cout ; from 7pF to 6pF
1. Remove x32 organization.
2. Remove -25/-22 speed bin
2.0
Nov. 17. 2003
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Nov. 2003
Rev 2.0
K7N403609B
K7N401809B
128Kx36 & 256Kx18 Pipelined NtRAM
TM
128Kx36 & 256Kx18-Bit Pipelined NtRAM
TM
FEATURES
• V
DD
=3.3V+0.165V/-0.165V Power Supply.
• V
DDQ
Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• Byte Writable Function.
• Enable clock and suspend operation.
• Single READ/WRITE control pin.
• Self-Timed Write Cycle.
• Three Chip Enable for simple depth expansion with no datacon-
tention.
•
Α
interleaved burst or a linear burst mode.
• Asynchronous output enable control.
• Power Down mode.
• TTL-Level Three-State Outputs.
• 100-TQFP-1420A Package.
• Operating in commeical and industrial temperature range.
GENERAL DESCRIPTION
The K7N403609B and K7N401809B are 4,718,592 bits Syn-
chronous Static SRAMs.
The NtRAM
TM
, or No Turnaround Random Access Memory
utilizes all the bandwidth in any combination of operating
cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation
and provides increased timing flexibility for incomming sig-
nals.
For read cycles, pipelined SRAM output data is temporarily
stored by an edge trigered output register and then released
to the output bufferes at the next rising edge of clock.
The K7N403609B and K7N401809B are implemented with
SAMSUNG′s high performance CMOS technology and is
available in 100pin TQFP packages. Multiple power and
ground pins minimize ground bounce.
FAST ACCESS TIMES
PARAMETER
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol
tCYC
tCD
tOE
-20
5.0
2.8
2.8
Unit
ns
ns
ns
LOGIC BLOCK DIAGRAM
A [0:16]or
A [0:17]
LBO
ADDRESS
REGISTER
A
2
~A
16
or A
2
~A
17
A
0
~A
1
BURST
ADDRESS
COUNTER
A′
0
~A′
1
128Kx36 , 256Kx18
MEMORY
ARRAY
CLK
CKE
CS
1
CS
2
CS
2
ADV
WE
K
WRITE
ADDRESS
REGISTER
WRITE
ADDRESS
REGISTER
BW
x
(x=a,b,c,d or a,b)
OE
ZZ
DQa
0
~ DQd
7
or DQa
0
~ DQb
8
DQPa ~ DQPd
CONTROL
LOGIC
K
DATA-IN
REGISTER
DATA-IN
REGISTER
K
CONTROL
REGISTER
CONTROL
LOGIC
K
OUTPUT
REGISTER
BUFFER
36 or 18
NtRAM
TM
and No Turnaround Random Access Memory are trademarks of Samsung,
-3-
Nov. 2003
Rev 2.0
K7N403609B
K7N401809B
PIN CONFIGURATION
(TOP VIEW)
BWb
128Kx36 & 256Kx18 Pipelined NtRAM
TM
BWa
CKE
ADV
N.C.
CS
2
N.C.
N.C.
A
6
N.C.
83
CLK
CS
1
CS
2
V
DD
V
SS
WE
OE
A
7
A
8
82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
81
A
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
N.C.
N.C.
N.C.
N.C.
V
SS
A
5
A
4
A
3
A
2
A
1
A
0
A
12
A
13
A
14
A
15
A
16
LBO
V
DD
PIN NAME
SYMBOL
A
0
- A
17
PIN NAME
Address Inputs
TQFP PIN NO.
32,33,34,35,36,37,
44,45,46,47,48,49
50,80,81,82,99,100
85
88
89
87
98
97
92
93,94
86
64
31
SYMBOL
V
DD
V
SS
N.C.
PIN NAME
TQFP PIN NO.
Power Supply(+3.3V) 14,15,16,41,65,66,91
17,40,67,90
Ground
1,2,3,6,7,25,28,29,30,
No Connect
38,39,42,43,51,52,53,
56,57,75,78,79,83,84
95,96
Data Inputs/Outputs
58,59,62,63,68,69,72,73,74
8,9,12,13,18,19,22,23,24
ADV
WE
CLK
CKE
CS
1
CS
2
CS
2
BWx(x=a,b)
OE
ZZ
LBO
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Power Sleep Mode
Burst Mode Control
DQa
0
~a
8
DQb
0
~b
8
A
11
V
DDQ
V
SSQ
Output Power Supply 4,11,20,27,54,61,70,77
(2.5V or 3.3V)
5,10,21,26,55,60,71,76
Output Ground
Notes :
1. The pin 83 is reserved for address bit for the 8Mb NtRAM.
2. A
0
and A
1
are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
-5-
A
17
50
N.C.
N.C.
N.C.
V
DDQ
V
SSQ
N.C.
N.C.
DQb
8
DQb
7
V
SSQ
V
DDQ
DQb
6
DQb
5
V
DD
V
DD
V
DD
V
SS
DQb
4
DQb
3
V
DDQ
V
SSQ
DQb
2
DQb
1
DQb
0
N.C.
V
SSQ
V
DDQ
N.C.
N.C.
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
K7N401809B(256Kx18)
A
10
N.C.
N.C.
V
DDQ
V
SSQ
N.C.
DQa
0
DQa
1
DQa
2
V
SSQ
V
DDQ
DQa
3
DQa
4
V
SS
V
DD
V
DD
ZZ
DQa
5
DQa
6
V
DDQ
V
SSQ
DQa
7
DQa
8
N.C.
N.C.
V
SSQ
V
DDQ
N.C.
N.C.
N.C.
Nov. 2003
Rev 2.0
FPGA/CPLD
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