KM29U64000IT datasheet, PDF - EEWORLD Datasheet

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KM29U64000IT: Description8M x 8 Bit NAND Flash Memory; Categorystorage storage; File Size334KB，26 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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KM29U64000IT Overview

8M x 8 Bit NAND Flash Memory

KM29U64000IT Parametric

Parameter Name	Attribute value
Maker	SAMSUNG
Parts packaging code	TSOP2
package instruction	TSOP2,
Contacts	44
Reach Compliance Code	unknow
ECCN code	3A991.B.1.A
Maximum access time	35 ns
Other features	HARDWARE DATA PROTECTION; 1M PROGRAM/ERASE CYCLES; DATA RETENTION 10 YEARS; BLOCK ERASE
Data retention time - minimum	10
JESD-30 code	R-PDSO-G40
length	18.41 mm
memory density	67108864 bi
Memory IC Type	FLASH
memory width	8
Number of functions	1
Number of terminals	40
word count	8388608 words
character code	8000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	8MX8
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL
Programming voltage	2.7 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	DUAL
width	10.16 mm

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KM29U64000T, KM29U64000IT

Document Title

8M x 8 Bit NAND Flash Memory

FLASH MEMORY

Revision History

Revision No. History

0.0

1.0

1.1

Initial issue.

Data Sheet, 1998

Data Sheet. 1999

1) Added CE don’ care mode during the data-loading and reading

Draft Date

April 10th 1998

July 14th 1998

April 10th 1999

Remark

Preliminary

Final

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the

specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the

SAMSUNG branch office near you.

KM29U64000T, KM29U64000IT

PRODUCT INTRODUCTION

FLASH MEMORY

The KM29U64000 is a 66Mbit(69,206,016 bit) memory organized as 16,384 rows by 528 columns. Spare sixteen columns are

located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data trans-

fer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells

that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 16

pages formed by one NAND structures, totaling 4,224 NAND structures of 16 cells. The array organization is shown in Figure 2. The

program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory

array consists of 1024 separately erasable 8K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the

KM29U64000.

The KM29U64000 has addresses multiplexed into 8 I/O′s. This scheme dramatically reduces pin counts and allows systems

upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through

I/O′s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address

Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle

except for Block Erase command which requires two cycles: one cycle for erase-setup and another for erase-execution after block

address loading. The 8M byte physical space requires 23 addresses, thereby requiring three cycles for byte-level addressing: col-

umn address, low row address and high row address, in that order. Page Read and Page Program need the same three address

cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used.

Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of

the KM29U64000.

Table 1. COMMAND SETS

Function

Sequential Data Input

Read ID

Reset

Page Program

Block Erase

Read Status

1st. Cycle

80h

00h/01h

(1)

50h

(2)

90h

FFh

10h

60h

70h

2nd. Cycle

D0h

Acceptable Command during Busy

NOTE

: 1. The 00H command defines starting address of the 1st half of registers.

The 01H command defines starting address of the 2nd half of registers.

After data access on the 2nd half of register by the 01h command, the status pointer is

automatically moved to the 1st half register(00h) on the next cycle.

2. The 50h command is valid only when the SE(pin 40) is low level.

KM29U64000T, KM29U64000IT

PIN DESCRIPTION

Command Latch Enable(CLE)

FLASH MEMORY

The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched

into the command register through the I/O ports on the rising edge of the WE signal.

Address Latch Enable(ALE)

The ALE input controls the path activation for address and input data to the internal address/data register.

Addresses are latched on the rising edge of WE with ALE high, and input data is latched when ALE is low.

Chip Enable(CE)

The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.

However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to standby

mode.

Write Enable(WE)

The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.

Read Enable(RE)

The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge

of RE which also increments the internal column address counter by one.

Spare Area Enable(SE)

The SE input controls the spare area selection when SE is high, the device is deselected the spare area during Read1, Sequential

data input and Page Program.

I/O Port : I/O 0 ~ I/O 7

The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z

when the chip is deselected or when the outputs are disabled.

Write Protect(WP)

The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when

the WP pin is active low.

Ready/Busy(R/B)

The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is

in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip

is deselected or when outputs are disabled.

Power Line(V

& V

The V

Q is the power supply for I/O interface logic. It is electrically isolated from main power line(V

=2.7V~3.6V) for supporting

5V tolerant I/O with 5V power supply at V

KM29U64000IT Related Products

	KM29U64000IT	KM29U64000T
Description	8M x 8 Bit NAND Flash Memory	8M x 8 Bit NAND Flash Memory
Maker	SAMSUNG	SAMSUNG
Parts packaging code	TSOP2	TSOP2
package instruction	TSOP2,	TSOP2,
Contacts	44	44
Reach Compliance Code	unknow	unknow
ECCN code	3A991.B.1.A	3A991.B.1.A
Maximum access time	35 ns	35 ns
Other features	HARDWARE DATA PROTECTION; 1M PROGRAM/ERASE CYCLES; DATA RETENTION 10 YEARS; BLOCK ERASE	HARDWARE DATA PROTECTION; 1M PROGRAM/ERASE CYCLES; DATA RETENTION 10 YEARS; BLOCK ERASE
Data retention time - minimum	10	10
JESD-30 code	R-PDSO-G40	R-PDSO-G40
length	18.41 mm	18.41 mm
memory density	67108864 bi	67108864 bi
Memory IC Type	FLASH	FLASH
memory width	8	8
Number of functions	1	1
Number of terminals	40	40
word count	8388608 words	8388608 words
character code	8000000	8000000
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS
Maximum operating temperature	85 °C	70 °C
organize	8MX8	8MX8
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSOP2	TSOP2
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL	PARALLEL
Programming voltage	2.7 V	2.7 V
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V
Minimum supply voltage (Vsup)	2.7 V	2.7 V
Nominal supply voltage (Vsup)	5 V	5 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	INDUSTRIAL	COMMERCIAL
Terminal form	GULL WING	GULL WING
Terminal pitch	0.8 mm	0.8 mm
Terminal location	DUAL	DUAL
width	10.16 mm	10.16 mm

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