The KS8995X is a highly integrated Layer-2 QoS (Quality of
Service) switch with optimized BOM (Bill of Materials) cost for
low port count, cost-sensitive 10/100Mbps switch systems. It
also provides an extensive feature set including three differ-
ent QoS priority schemes, a dual MII interface for BOM cost
reduction, rate limiting to offload CPU tasks, software and
hardware power-down, a MDC/MDIO control interface and
port mirroring/monitoring to effectively address both current
and emerging Fast Ethernet applications.
The KS8995X contains five 10/100 transceivers with pat-
ented mixed-signal low-power technology, five MAC (Media
Access Control) units, a high-speed non-blocking switch
fabric, a dedicated address lookup engine, and an on-chip
frame buffer memory.
All PHY units support 10BaseT and 100BaseTX. In addition,
two of the PHY units support 100BaseFX (Ports 4 and 5).
All support documentation can be found on Micrel’s web site
at www.micrel.com.
Features
• Integrated switch with five MACs and five Fast Ethernet
transceivers fully compliant to IEEE 802.3u standard
• Shared memory based switch fabric with fully non-
blocking configuration
• 10BaseT, 100BaseTX and 100BaseFX modes (FX in
Ports 4 and 5)
• Dual MII configuration: MII-Switch (MAC or PHY mode
MII) and MII-P5 (PHY mode MII)
• VLAN ID tag/untag options, per-port basis
• Enable/disable option for huge frame size up to 1916
bytes per frame
• Broadcast storm protection with percent control – global
and per-port basis
• Optimization for fiber-to-copper media conversion
• Full-chip hardware power-down support (register
configuration not saved)
• Per-port-based software power-save on PHY (idle link
detection, register configuration preserved)
• QoS/CoS packets prioritization supports: per port,
802.1p and DiffServ based
Functional Diagram
Auto
MDI/MDIX
Auto
MDI/MDIX
Auto
MDI/MDIX
Auto
MDI/MDIX
Auto
MDI/MDIX
MII-P5
MDC, MDI/O
MII-SW or SNI
LED0[5:1]
LED1[5:1]
LED2[5:1]
10/100
T/Tx 1
10/100
T/Tx 2
10/100
T/Tx 3
10/100
T/Tx/Fx 4
10/100
T/Tx/Fx 5
10/100
MAC 1
FIFO, Flow Control, VLAN Tagging, Priority
1K look-up
Engine
Queue
Mgmnt
Buffer
Mgmnt
Frame
Buffers
10/100
MAC 2
10/100
MAC 3
10/100
MAC 4
10/100
MAC 5
SNI
LED I/F
Control
Registers
EEPROM
I/F
Micrel, Inc. • 1849 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 944-0970 • http://www.micrel.com
December 2003
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Micrel
Features
(continued)
• 802.1p/q tag insertion or removal on a per-port basis
(egress)
• Port-based VLAN support
• MDC and MDI/O interface support to access the MII
PHY control registers (not all control registers)
• MII local loopback support
• On-chip 64Kbyte memory for frame buffering (not
shared with 1K unicast address table)
• 1.4Gbps high-performance memory bandwidth
• Wire-speed reception and transmission
• Integrated look-up engine with dedicated 1K unicast
MAC addresses
• Automatic address learning, address aging and address
migration
• Full-duplex IEEE 802.3x and half-duplex back pressure
flow control
• Comprehensive LED support
• 7-wire SNI support for legacy MAC interface
• Automatic MDI/MDI-X crossover for plug-and-play
• Disable automatic MDI/MDIX option
• Low power
Core: 1.8V
I/O: 2.5 or 3.3V
• 0.18µm CMOS technology
• Commercial temperature range: 0°C to +70°C
• Available in 128-pin PQFP package
Applications
•
•
•
•
•
•
•
•
•
Broadband gateway/firewall/VPN
Integrated DSL or cable modem multi-port router
Wireless LAN access point plus gateway
Home networking expansion
Standalone 10/100 switch
Hotel/campus/MxU gateway
Enterprise VoIP gateway/phone
FTTx customer premise equipment
Media converter
Ordering Information
Part Number Temperature Range Package
KS8995X
KSZ8995X
0°C to +70°C
0°C to +70°C
128-Pin PQFP
128-Pin PQFP Lead Free
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Revision History
Revision
1.08
1.09
Date
4/01/02
5/20/02
Summary of Changes
Created.
Changed MII setting descriptions. Changed pu/pd descriptions for SMRXD2.
Changed pu/pd description for forced flow control.
Edited large packet sizes back in, also in
“Register 4.”
Added in typical supply current numbers for 100BaseTX and 10BaseTX operation.
Added in note for illegal half-duplex, force flow control.
Added extra X1 clock input description.
Updated to chip only current numbers.
“Register 4”
and
“Pin Description”
PMRXER correction.
Changed SMRXC and SMTXC to I/O. Input in MAC mode, output in PHY mode MII. Changed polarity of
TXP and TXM pins. “Electrical Characteristics” modified current consumption to chip only numbers.
Added description for no dropped packets in half duplex mode. Added recommended operating
conditions. Added Idle mode current consumption. Added
“Selection of Isolation Transformers.”
Added 3.01kΩ resistor instructions for ISET
“Pin Description.”
Changed Polarity of transmit pairs in
“Pin Description.”
Changed description for register 2, bit 1, in
“Register Description.”
Added
“Reset Tming.”
Added
“QoS Description.” “Register 3”
changed 802.1x to 802.3x.
“Register 6”
changed default column to disable flow control for pull-down, and enable flow control for pull up.
“Register 29”
and
“MIIM Register 0”
indicate loop back is at the PHY
Removed caption under table in
“Register 18.”
Changed definition of MDI/MDIX in
“Register 29,”
“Register 30,” “MIIM Register 0.”
Refer to 8995XA data sheet.
Convert to new format.
1.10
10/9/02
1.11
1.12
1.13
10/24/02
5/20/03
8/29/03
December 2003
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Table of Contents
System Level Applications ..............................................................................................................................................................
100BaseFX Signal Detection ................................................................................................................................................... 20
100BaseFX Far End Fault ....................................................................................................................................................... 20
Power Management ................................................................................................................................................................ 20
MDI/MDI-X Auto Crossover ..................................................................................................................................................... 20
Address Look Up ..................................................................................................................................................................... 21
MAC (Media Access Controller) Operation ............................................................................................................................. 22
Inter-Packet Gap ............................................................................................................................................................. 22
Late Collision .................................................................................................................................................................. 22
Flow Control .................................................................................................................................................................... 22
Half-Duplex Back Pressure ............................................................................................................................................. 22
MII Interface Operation ..................................................................................................................................................................
QoS Support ............................................................................................................................................................................ 25
Rate Limit Support ................................................................................................................................................................... 27
I2C Master Serial Bus Configuration ............................................................................................................................... 28
MII Management Interface (MIIM) ..................................................................................................................................................
Global Registers ...................................................................................................................................................................... 29
Register 2 (0x02): Global Control 0 ................................................................................................................................ 29
Register 3 (0x03): Global Control 1 ................................................................................................................................ 30
Register 4 (0x04): Global Control 2 ................................................................................................................................ 31
Register 5 (0x05): Global Control 3 ................................................................................................................................ 31
Register 6 (0x06): Global Control 4 ................................................................................................................................ 32
Register 7 (0x07): Global Control 5 ................................................................................................................................ 32
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Register 8 (0x08): Global Control 6 ................................................................................................................................ 32
Register 9 (0x09): Global Control 7 ................................................................................................................................ 32
Register 10 (0x0A): Global Control 8 ............................................................................................................................. 32
Register 11 (0x0B): Global Control 9 ............................................................................................................................. 33
Port Registers .......................................................................................................................................................................... 33
Register 16 (0x10): Port 1 Control 0 .............................................................................................................................. 33
Register 17 (0x11): Port 1 Control 1 .............................................................................................................................. 34
Register 18 (0x12): Port 1 Control 2 .............................................................................................................................. 34
Register 19 (0x13): Port 1 Control 3 .............................................................................................................................. 35
Register 20 (0x14): Port 1 Control 4 .............................................................................................................................. 35
Register 21 (0x15): Port 1 Control 5 .............................................................................................................................. 35
Register 22 (0x16): Port 1 Control 6 .............................................................................................................................. 35
Register 23 (0x17): Port 1 Control 7 .............................................................................................................................. 36
Register 24 (0x18): Port 1 Control 8 .............................................................................................................................. 36
Register 25 (0x19): Port 1 Control 9 .............................................................................................................................. 36
Register 26 (0x1A): Port 1 Control 10 ............................................................................................................................ 36
Register 27 (0x1B): Port 1 Control 11 ............................................................................................................................ 37
Register 28 (0x1C): Port 1 Control 12 ............................................................................................................................ 37
Register 29 (0x1D): Port 1 Control 13 ............................................................................................................................ 38
Register 30 (0x1E): Port 1 Status 0 ............................................................................................................................... 39
Register 31 (0x1F): Port 1 Status 1 ................................................................................................................................ 39
Advanced Control Registers .................................................................................................................................................... 39
Register 96 (0x60): TOS Priority Control Register 0 ...................................................................................................... 39
Register 97 (0x61): TOS Priority Control Register 1 ...................................................................................................... 39
Register 98 (0x62): TOS Priority Control Register 2 ...................................................................................................... 39
Register 99 (0x63): TOS Priority Control Register 3 ...................................................................................................... 39
Register 100 (0x64): TOS Priority Control Register 4 .................................................................................................... 39
Register 101 (0x65): TOS Priority Control Register 5 .................................................................................................... 39
Register 102 (0x66): TOS Priority Control Register 6 .................................................................................................... 40
Register 103 (0x67): TOS Priority Control Register 7 .................................................................................................... 40
Register 104 (0x68): MAC Address Register 0 .............................................................................................................. 40
Register 105 (0x69): MAC Address Register 1 .............................................................................................................. 40
Register 106 (0x6A): MAC Address Register 2 .............................................................................................................. 40
Register 107 (0x6B): MAC Address Register 3 .............................................................................................................. 40
Register 108 (0x6C): MAC Address Register 4 ............................................................................................................. 40
Register 109 (0X6D): MAC Address Register 5 ............................................................................................................. 40
Register 0: MII Control ................................................................................................................................................... 40
Register 1: MII Status .................................................................................................................................................... 41
Register 2: PHYID HIGH ................................................................................................................................................ 41
Register 5: Link Partner Ability ....................................................................................................................................... 42
Absolute Maximum Ratings ..........................................................................................................................................................
Selection of Isolation Transformers .............................................................................................................................................
50
Package Information ......................................................................................................................................................................
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