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IDT72V18160L10PFGI

Description
FIFO, 32KX16, 6.5ns, Synchronous, CMOS, PQFP80, TQFP-80
Categorystorage    storage   
File Size238KB,26 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
Download Datasheet Parametric View All

IDT72V18160L10PFGI Overview

FIFO, 32KX16, 6.5ns, Synchronous, CMOS, PQFP80, TQFP-80

IDT72V18160L10PFGI Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
Parts packaging codeQFP
package instructionTQFP-80
Contacts80
Reach Compliance Codecompli
ECCN codeEAR99
Maximum access time6.5 ns
period time10 ns
JESD-30 codeS-PQFP-G80
JESD-609 codee3
length14 mm
memory density524288 bi
memory width16
Humidity sensitivity level3
Number of functions1
Number of terminals80
word count32768 words
character code32000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize32KX16
ExportableYES
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)3.45 V
Minimum supply voltage (Vsup)3.15 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMATTE TIN
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width14 mm
Base Number Matches1
3.3V MULTIMEDIA FIFO
16 BIT V-III, 32 BIT Vx-III FAMILY
UP TO 1 Mb DENSITY
IDT72V15160
IDT72V16160
IDT72V17160
IDT72V18160
IDT72V19160
IDT72V14320
IDT72V15320
IDT72V16320
IDT72V17320
IDT72V18320
IDT72V19320
FEATURES:
Choose among the following memory organizations: Commercial
V-III
Vx-III
IDT72V15160 - 4,096 x 16
IDT72V16160 - 8,192 x 16
IDT72V17160 - 16,384 x 16
IDT72V18160 - 32,768 x 16
IDT72V19160 - 65,536 x 16
IDT72V14320 - 1,024 x 32
IDT72V15320 - 2,048 x 32
IDT72V16320 - 4,096 x 32
IDT72V17320 - 8,192 x 32
IDT72V18320 - 16,384 x 32
IDT72V19320 - 32,768 x 32
Up to 100 MHz Operation of the Clocks
5V input tolerant
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
Program programmable flags through serial input
Output enable puts data outputs into high impedance state
JTAG port, provided for Boundary Scan function (PBGA Only)
Available in a 80-pin (V-III) Thin Quad Flat Pack, 128-pin(Vx-III)
Thin Quad Flat Pack (TQFP) or a 144-pin (Vx-III) Plastic Ball Grid
Array (PBGA) (with additional features)
Industrial temperature range (–40°C to +85°C)
°
°
High-performance submicron CMOS technology
FUNCTIONAL BLOCK DIAGRAM
*
Available on the Vx-III PBGA package only.
MRS
WCLK
WEN
PRS
RCLK
REN
OE
D0 - Dn
Data In
x16, x32
FIFO ARRAY
Q0 - Qn
Data Out
x16, x32
WRITE
CONTROL
RESET LOGIC
READ
CONTROL
*
*
**
*
TCK
TRST
TMS
TDI
TDO
JTAG CONTROL
(BOUNDARY
SCAN)
*
LD
SEN
SI
PFM
FLAG LOGIC
FSEL1
EF
FSEL0
HF
PAE
FF
PAF
6163 drw01
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
NOVEMBER 2003
DSC-6163/3
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