AN91
Si3200 P
O W E R
O
F F L O A D
C
I R C U I T
Introduction
This application note presents a method of offloading
power dissipation from the Si3200 linefeed device and
onto either an external linear regulator or an external
resistor.
A design method to select the optimal voltage drop
across the external power offload circuit based upon
system requirements is also presented. Once the
optimal external circuit voltage drop has been
determined, the selection of the Zener diode in Figure 1
or the R
offload
resistors in Figure 2 is straightforward.
The solutions presented are intended for applications in
which a single battery supply is available, and it is
desirable to derive a lower battery voltage from this
single supply to minimize power dissipation on shorter
loops.
In this document, the system-supplied higher magnitude
voltage is referred to as VBHI, and the derived lower
magnitude voltage is referred to as VBLO. Figure 1
shows the linear regulator power offload circuit while
Figure 2 shows the external resistor power offload
circuit.
Si322x
Battery Sense Logic
Battery Control Logic
1
SVBATa
SVBATb
16
BATSELa
49
BATSELb
32
40.2k
BATSEL
40.2k
BATSEL
9
9
Battery
Select Circuit
Line Feed
Circuit
Line Feed
Circuit
Battery
Select Circuit
806k
VBATL
6
VBAT
4
0.1uF
806k
VBATL
6
VBAT
4
0.1uF
VBATH
5
VBATH
5
0.1uF
0.1uF
Si3200
Channel 0
Si3200
Channel 1
MJD2955
CMPZ4707
Vz = 20V
VBHI = -56Vdc
Linear Regulator Offload Circuit
Figure 1. Linear Regulator Power Offload Circuit
Rev. 0.1 6/03
Copyright © 2003 by Silicon Laboratories
AN91
AN91
Design Method
The following sections present a design method for the
linear regulator and resistor power offload circuits.
System Requirements
Table 1 enumerates the system requirements that must
be known to proceed with the power offload circuit
design. The values for each of these parameters stem
from the specific customer application and its unique
requirements.
Si322x
Battery Sense Logic
Battery Control Logic
SVBATa
BATSELa
40.2k
BATSEL
BATSELb
1
SVBATb
16
49
32
40.2k
BATSEL
9
9
Battery
Select Circuit
Line Feed
Circuit
Line Feed
Circuit
Battery
Select Circuit
806k
VBATL
6
VBAT
4
0.1uF
806k
VBATL
6
VBAT
4
0.1uF
VBATH
5
VBATH
5
0.1uF
0.1uF
Si3200
Channel 0
Si3200
Channel 1
VBHI = -56Vdc
Resistor Offload Circuit
Figure 2. External Resistor Power Offload Circuit
Table 1. System Requirements
Parameter
Maximum Ambient Temperature
Loop Current (ILIM)
Bias Current (SBIAS)
Telephone dc Resistance (typ.)
Maximum Loop Length
Wire dc Resistance per unit length
Battery Supply Voltage
Overhead Voltages (V
CM
+ V
OV
)
Symbol
T
a (max)
I
lim
I
bias
R
ph
L
w (max)
R
w
VBHI
V
oh
Units
°C
mA
mA
Ω
feet/meters
Ω/foot
or
Ω/meter
Volts
Volts
2
Rev. 0.1
AN91
Maximum Si3200 Power Dissipation
The maximum power dissipation for the Si3200 linefeed
device is established from its specified maximum
junction temperature (T
j(max)
) and junction-to-ambient
thermal impedance (θ
ja
) along with the customer-
supplied expected maximum ambient temperature
(T
a(max)
).
P
d
(
max
)
T
j
(
max
)
–
T
a
(
max
)
= --------------------------------------------
θ
ja
P
Si3200
is the power dissipated in the Si3200 in watts.
I
lim
is the required off-hook loop current as set by the
ILIM register in amps.
I
bias
is the required bias current as set by the ABIAS
field in the SBIAS register in amps.
V
BAT
is the battery voltage (may be set to VBHI or
VBLO, depending on loop length) in volts.
R
w
is the resistance per linear foot (or linear meter) of
the wire (e.g., 24AWG or 26AWG wire).
L
w
is the loop length in feet or meters.
R
ph
is the off-hook dc resistance of the telephone.
V
BAT
may be either VBHI or VBLO depending on which
battery voltage the Si3200 is using. The Si322x devices
feature automatic battery selection, which is based
upon the measurement of the dc voltage present on the
RING terminal. "Battery Switching Threshold Settings‚"
on page 5 describes a method for selecting the correct
value for the BATHTH, BATLTH, and BATLPF RAM
locations, which control the voltage thresholds at which
the system will switch battery voltage and the filtering of
the RING dc signal. These RAM locations must be
programmed with the correct values that optimize the
switching point between VBHI and VBLO.
When the system is using the lower battery voltage
(VBLO), the worst-case power dissipation in the Si3200
occurs when the loop length is zero. If the loop length is
zero, the R
w
x L
w
term in Equation 2 vanishes resulting
in Equation 3 .
P
Si3200
=
(
I
LIM
+
I
BIAS
) ×
V
BAT
–
R
ph
×
I
LIM
2
Equation 1.Maximum Power Dissipation
Table 2 provides the thermal impedance of the Si3200
device and its maximum junction temperature.
To achieve the thermal impedance (θ
ja
) stated in
Table 2, it is necessary to provide a suitably-designed
PCB heat slug (copper fill) structure under the Si3200
package. The heat slug must be, as much as possible,
contiguous with the system GND fill on the top circuit
layer underneath the Si3200 package. The heat slug
should be connected with a row of eight vias that are at
least 10 mils (~0.25 mm) in diameter to inner PCB
circuit layers, such as the ground plane layer, and to the
bottom circuit side GND fill. The Si3220DC-EVB Rev. 2
evaluation board layout from Silicon Laboratories
provides an example of a suitable heat slug design for
the Si3200.
Table 2. Si3200 Thermal Parameters
Parameter
θ
ja
T
j(max)
Value
55
140
Units
°C/Watt
°C
Equation 3.Power Dissipated in the Si3200
(at zero loop length)
Replacing P
Si3200
in Equation 3 with P
d(max)
and V
BAT
with VBLO, an expression for VBLO is obtained as
shown in Equation 4.
P
d
(
max
)
+
R
ph
×
I
LIM
-
VBLO
= -------------------------------------------------------
I
LIM
+
I
BIAS
2
The primary objective of the power offload circuit is to
ensure that the power dissipation in the Si3200 device
will remain under P
d(max)
at up to the maximum required
ambient temperature under the required operating
conditions of loop length, battery voltage, loop current,
and bias current.
Optimal VBLO Determination
The power dissipation in the Si3200 device, during the
forward/reverse active off-hook state is obtained from
Equation 2 below.
P
Si3200
=
(
I
LIM
+
I
BIAS
) ×
V
BAT
–
(
R
w
×
L
w
+
R
ph
) ×
I
LIM
2
Equation 4.VBLO
Equation 4 yields the low battery voltage (VBLO) at
which the power dissipation in the Si3200 will equal
P
d(max)
at zero loop length. Actually, it is desired to have
P
Si3200
under P
d(max)
by some margin. Hence, Equation
4 is modified to include a factor to scale P
d(max)
to
provide margin, resulting in Equation 5. For example, let
k = 0.80 so that power dissipation in the Si3200 will be
at 80% of P
d(max)
when operating from VBLO on a zero
Equation 2.Power Dissipated in Si3200 Linefeed
where:
Rev. 0.1
3
AN91
loop length line.
k
×
P
d
(
max
)
+
R
ph
×
I
LIM
VBLO
= -----------------------------------------------------------------
I
LIM
+
I
BIAS
2
typically rated at 350 mW, which is ample power
dissipation capacity for this application.
The power dissipated in the transistor used in the linear
regulator is obtained using Equation 9 (with both
channels simultaneously off-hook – hence the 2x factor
in Equation 9). The designer must ensure that the
selected transistor and its corresponding PCB footprint
can adequately handle the power dissipated with some
margin
while
taking
into
consideration
the
manufacturer’s rated P
d(max)
and its corresponding
derating as ambient temperature increases. For most
applications, a PNP transistor, such as the ON
Semiconductor, MJD2955, in a DPAK package or
equivalent, is well suited for this application, provided
that a suitable PCB heat slug (copper fill) is designed
under the transistor package. (See "Typical Design
Example‚" on page 6).
P
Q
=
2
× (
VBHI
–
VBLO
) × (
I
LIM
+
I
BIAS
)
Equation 5.VBLO (with margin factor)
The selection of VBLO may require several iterations in
order to derive the optimal solution that ensures power
dissipation in both the Si3200 and the offload circuit
under all operating conditions. The “Power Offload Tool”
section of this document describes a Power Offload
Calculation tool to facilitate the iterative process to
determine the optimal VBLO.
Power Offload Circuit Component
Selection
Once the optimal VBLO has been determined, it is a
simple matter to determine the resistor value needed for
the resistive power offload circuit or the Zener diode
voltage for the linear regulator offload circuit.
Resistive Offload Circuit
The value of the resistor used in the resistive offload
circuit is readily computed from Equation 6.
VBHI
–
VBLO
-
R
offload
= -------------------------------------------
I
LIM
+
I
BIAS
Equation 9.Transistor Power Dissipation
Equation 10 provides the worst-case power dissipation
in the Zener diode based on the rated Zener voltage
and the rated minimum current gain (β
min
) of the
transistor for the case when both channels are
simultaneously off-hook. The Central Semiconductor
CMPZ4678-CMPZ4717 Zener diode family in an SOT-
23 package provides adequate power dissipating
margin. (See "Typical Design Example‚" on page 6).
I
LIM
+
I
BIAS
-
P
Z
=
2
×
V
Z
×
-----------------------------
β
min
Equation 6.Offload Resistor Calculation
Choose the standard 5% resistor value nearest to the
calculated R
offload
value.
The power dissipation in the offload resistor is obtained
from Equation 7:
P
offload
=
R
offload
× (
I
LIM
+
I
BIAS
)
2
Equation 10.Zener Diode Power Dissipation
Equation 7.Resistor Power Dissipation
Choose a resistor power rating that can accommodate
P
offload
plus an adequate margin.
Thermal Considerations
The system designer must carefully consider the PCB
placement of the offload resistor or the linear regulator
so as to optimize system heat dissipation. The offload
circuit (resistor or linear regulator) is not electrically
required to be placed close to pin 6 (VBATL) of the
Si3200 and should therefore be placed up to two inches
(approximately 5 cm) away from the Si3200 device,
thus, physically separating components that are
dissipating appreciable power.
To minimize the resistor cost, the offload resistors can
be through-hole instead of SMT. To further spread heat
dissipation and reduce the power rating of the individual
resistors, the offload resistors can be split into two or
more equal-value resistors whose parallel combination
forms the desired R
offload
value.
Linear Regulator Offload Circuit
The nominal Zener diode voltage is obtained from
VBLO, and the typical V
be
voltage drop in a bipolar
transistor.
V
z
=
VBHI
–
VBLO
–
0.6V
Equation 8.Zener Voltage
Choose a 5% Zener diode with nominal Zener voltage
(Vz) as close as possible to the value determined by
Equation 8. Zener diodes in SOT23 packages are
4
Rev. 0.1
AN91
In the case of the linear regulator, the system designer
must consider the manufacturer’s rated maximum
power dissipation of the Zener diode and transistor and
ensure that these ratings are not exceeded under all
expected operating conditions. The manufacturer’s
recommended PCB footprint for the Zener diode and
transistor must be followed to ensure proper heat
dissipation.
As with any line card system design, the designer must
take into consideration proper ventilation and airflow to
carry heat away from power-dissipating components in
the system and to ensure that the maximum allowable
ambient temperature within the system enclosure is not
exceeded under all expected operating conditions.
When VBLO can no longer satisfy Equation 11, VBHI
must be selected.
Since the battery switching mechanism monitors the dc
voltage at the RING terminal (TIP in reverse active
mode), and the RING voltage with respect to system
GND already includes V
CM
, the switching threshold is
obtained from Equation 13.
V
thres
=
VBLO
–
V
OV
Equation 13.Battery Switching Threshold Voltage
The RAM locations, BATHTH and BATLTH, can assume
any value in the range from 0 to 160.2 in Volts. One LSB
of BATHTH or BATLTH is 628 mV. The values for
BATHTH and BATLTH occupy bits 7 through 14 in their
corresponding RAM locations and must be shifted up by
7 bit positions, hence the multiplication by 2
7
in
Equations 14 and 15.
Equations 14 and 15 provide a means of calculating
BATHTH and BATLTH, which provides for two LSBs of
hysteresis (2 x 0.628 = 1.256V).
V
thres
7
-
BATLTH
=
2
×
DEC2HEX
--------------- +
1
0.628
Battery Switching Threshold
Settings
The Si322x device provides two threshold registers that
allow software to select the thresholds at which the
system switches battery supply. Two thresholds are
used to provide hysteresis. The value of the BATHTH
RAM location determines the RING dc voltage at which
the system switches from VBLO to VBHI upon going on-
hook. The value of BATLTH determines the RING dc
voltage at which the system switches from VBHI to
VBLO upon going off-hook.
The value of BATLPF determines corner frequency of
the digital low-pass filter used to filter the RING dc
voltage for the purposes of comparing against the set
thresholds.
For a given loop condition, the SLIC must be able to
supply enough voltage to the loop (V
tr
) in the off-hook
state, and maintain the required overhead voltage
(V
oh
= V
cm
+ V
ov
). This requirement is expressed in
Equation 11 (see “DC Feed Characteristics” in the
Si3220/Si3225 Data Sheet for a more detailed
explanation of V
OV
and V
CM
.)
VBAT
≥
V
tr
+
V
CM
+
V
OV
Equation 14.BATHTH
V
thres
7
-
BATHTH
=
2
×
DEC2HEX
--------------- –
1
0.628
Equation 15.BATLTH
The value of BATLPF is obtained from Equation 16,
where f is the desired cut-off frequency for the low-pass
filter. BATLPF occupies bits 3 through 15 and must be
shifted up 3 bit positions, hence the multiply by 2
3
in
Equation 16. Typically, f is set to 10 Hz, which yields
BATLPF = 0xA10.
3
2
× π ×
f
×
4096
-
BATLPF
=
2
×
D EC2HEX
---------------------------------------
800
Equation 11.Battery Voltage Requirement
V
tr
is the product of ILIM and the total dc resistance of
the loop, as shown in Equation 12.
V
tr
=
I
LIM
× (
R
w
×
L
w
+
R
ph
)
Equation 16.BATLPF
Power Offload Tool
This application note is bundled with an Excel file titled
“Si3200_power_calc.xls”.
The bundled Excel file provides a very useful tool for
analyzing the power dissipation of the Si3200 as a
function of loop length and other user-entered
parameters. The user enters the desired values for the
various parameters at the top of the worksheet and the
Equation 12.TIP-RING Voltage
The optimal battery-switching threshold is selected
based upon the ability of VBLO to satisfy Equation 11.
So long as VBLO is able to satisfy the requirement in
Equation 11, the VBLO battery source must be selected.
Rev. 0.1
5
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