BELASIGNA 250
High-Performance
Programmable Audio
Processing System
BELASIGNA
®
250 is a complete programmable audio processing
system, designed specifically for ultra−low−power embedded and
portable digital audio systems. This high−performance chip builds on
the architecture and design of BELASIGNA 200 to deliver
exceptional sound quality along with unmatched flexibility.
BELASIGNA 250 incorporates a full audio signal chain, from
stereo 16−bit A/D converters or digital interfaces to accept the signal,
through the fully flexible digital processing architecture, to stereo
analog line−level or direct digital power outputs that can connect
directly to speakers.
BELASIGNA 250 features flexible clocking options and smart
power management features including a soft power−down mode. Two
DSP subsystems operate concurrently: the RCore, which is a fully
software programmable DSP core, and the weighted overlap−add
(WOLA) filterbank coprocessor, which is a dedicated, configurable
processor that executes time−frequency domain transforms and other
vector− based computations. A full range of other hardware−assisted
features, such as audio−targeted DMA complete the system.
A comprehensive and easy−to−use suite of development tools,
hands−on training and full technical support are available to enable
rapid development and introduction of highly differentiated products
in record time.
Key Features
Introduction
http://onsemi.com
LFBGA−64
7x7
CASE 566AF
CABGA−57
5x5
CASE 566AA
MARKING DIAGRAMS
XXXXYZZ
BELASIGNA
250
0W888−002
AAAA
•
Unique Parallel−processing Architecture:
A Complete DSP−based,
Mixed−signal Audio System Consisting of a 16−bit Fully
Programmable Dual−Harvard 16−bit DSP Core, a Patented,
High−resolution Block Floating−point WOLA Filterbank Coprocessor,
and an Input/Output Processor (IOP) along with Several Peripherals
and Interfaces which Optimize the Architecture for Audio Processing
Integrated Converters and Powered Output:
Minimize Need for
External Components
Ultra−low Power Consumption:
Under 5 mA at 20 MHz to Support
Advanced Operations; 1.8 V Supply Voltage
“Smart” Power Management:
Including Low Current Standby
Mode Requiring Only 0.05 mA
Flexible Clocking Architecture:
Supports Speeds up to 50 MHz
Full Range of Configurable Interfaces:
Including: I
2
S, PCM,
UART, SPI, I
2
C, TWSS, GPIO
Excellent Fidelity:
88 dB System Dynamic Range, Exceptionally
Low System Noise and Low Group Delay
Support for IP Protection:
to Prevent Unauthorized Access to
Algorithms and Data
Available in CABGA and LFBGA Package Options
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
1
XXXXYZZ
B−250
0W633
AAAA
•
•
•
•
•
•
•
•
•
0W888−002 = 64 LFBGA Option
0W633 = 57 CABGA Option
XXXX = Date Code
Y
= Assembly Plant Identifier
ZZ
= Traceability Code
AAAA = Country of Assembly
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 28 of this data sheet.
©
Semiconductor Components Industries, LLC, 2015
January, 2015 − Rev. 10
Publication Order Number:
B250/D
BELASIGNA 250
Figures and Data
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage at any input pin
Operating supply voltage (Note 1)
Operating temperature range (Note 2)
Storage temperature range
Caution: Class 2 ESD Sensitivity, JESD22−A114−B (2000 V)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Below 1.05 V audio performance will be degraded.
2. Parameters may exceed listed tolerances when out of the temperature range 0 to 50°C.
Min
−0.3
0.9
−40
−40
Max
2.2
2.0
85
125
Unit
V
V
°C
°C
http://onsemi.com
2
BELASIGNA 250
Electrical Performance Specifications
The parameters in Table 2 do not vary with WOLA filterbank configuration. The tests were performed at 20°C with a clean
1.8 V supply voltage. BELASIGNA 250 was running in high voltage mode (VDDC = 1.8 V). The system clock (SYS_CLK)
was set to 5.12 MHz and a sampling frequency of 16 kHz was used with MCLK was set to 1.28 MHz.
Parameters marked as screened are tested on each chip. Other parameters are qualified but not tested on every part.
Table 2. ELECTRICAL SPECIFICATIONS
Description
OVERALL
Supply voltage
Current consumption
V
BAT
I
BAT
SYS_CLK = 1.28 MHz,
sample rate = 16 kHz
5.12 MHz, 16 kHz
19.2 MHz, 16 kHz
49.152 MHz, 16 kHz
49.152 MHz, 48 kHz
VREG (1
mF
External Capacitor)
Regulated voltage output
Regulator PSRR
Load current
Load regulation
Line regulation
VDBL (1
mF
External Capacitor)
Regulated doubled voltage output
Regulator PSRR
Load current
Load regulation
Line regulation
VDDC (1
mF
External Capacitor)
Digital supply voltage output
VDDC
LV mode (VREG)
DV mode (VDBL)
Regulator PSRR
VDDC
PSRR
LV mode; 1 kHz
DV mode; 1 kHz
Load current
VDDC (1
mF
External Capacitor)
Load regulation
LOAD
REG
LV mode
DV mode
Line regulation
LINE
REG
LV mode
DV mode
POWER−ON−RESET (POR)
POR startup voltage
POR shutdown voltage
3.
4.
5.
6.
VDDC
STARTUP
VDDC
SHUTDOWN
0.78
0.76
0.83
0.81
0.88
0.86
V
V
−
−
−
−
5
150
1.5
5
10
250
10
10
mV/mA
mV/mA
mV/V
mV/V
√
√
I
LOAD
All modes
0.9
1.8
20
40
−
1.0
2.0
28
48
−
1.1
2.2
−
−
3.5
V
V
dB
dB
mA
√
√
VDBL
VDBL
PSRR
I
LOAD
LOAD
REG
LINE
REG
1 kHz
1.9
45
−
−
−
2.0
50
−
120
5
2
200
10
2.1
V
dB
mA
mV/mA
mV/V
√
√
V
REG
V
REG_PSRR
I
LOAD
LOAD
REG
LINE
REG
1 kHz
0.95
50
−
−
−
1.00
55
−
11
2
2
20
5
1.05
V
dB
mA
mV/mA
mV/V
√
0.9
(Note 3)
−
−
−
−
−
1.8
650
1
5
10
13
2.0
−
−
−
−
−
V
mA
mA
mA
mA
mA
Symbol
Conditions
Min
Typ
Max
Units
Screened
Audio performance will be degraded below 1.05 V.
Measured with a = 12 dB input signal.
Input stage delay is inversely proportional to sampling frequency.
Max voltage should be limited to 2.2 V peak regardless of VDDC. Protection diodes will be enabled above this voltage.
http://onsemi.com
3
BELASIGNA 250
Table 2. ELECTRICAL SPECIFICATIONS
(continued)
Description
POWER−ON−RESET (POR)
POR hysteresis
POR duration
INPUT STAGE
Analog input voltage
Preamplifier gain tolerance
Preamplifier gain mismatch be-
tween channels
Input impedance
R
IN
V
IN
PAG
1 kHz
1 kHz
0 dB preamplifer gain
Non−zero preamplifier gains
Input referred noise
IN
IRN
Unweighted,
20 Hz to 8 kHz BW
Preamplifier setting:
0 dB
12 dB
15 dB
18 dB
21 dB
24 dB
27 dB
30 dB
1 kHz, 20 Hz to 8 kHz BW
Preamplifier setting:
0 dB
12 dB
15 dB
18 dB
21 dB
24 dB
27 dB
30 dB
Any valid preamplifier gain,
1 kHz
0
−1.5
−1
−
400
−
−
−
250
550
2
1.5
1
−
700
V
dB
dB
kW
kW
mVrms
√
√
POR
HYSTERESIS
T
POR
10
5
16
10
22
15
mV
ms
Symbol
Conditions
Min
Typ
Max
Units
Screened
−
−
−
−
−
−
−
−
40
12
8
6
4.5
4
3.5
3
55
14
11
8
5.5
5
4.5
4
dB
Input dynamic range
IN
DR
85
84
84
83
82
81
80
78
−
−
88
87
87
86
85
84
83
81
−63
200
−
−
−
−
−
−
−
−
−60
−
dB
ms
√
Input peak THD+N (Note 4)
Input stage delay (Note 5)
DIRECT DIGITAL OUTPUT
Maximum load current
IN
THDN
I
DO
Normal mode
High power mode
−
−
−
−
90
−
−
9
5
93
−79
13
25
11
6
−
−76
Vbat
mA
mA
W
W
dB
dB
V
Output impedance
R
DO
Normal mode
High power mode
Output dynamic range
Output THD+N
Output voltage
ANALOG OUTPUT STAGE
Analog output voltage
3.
4.
5.
6.
DO
DR
DO
THDN
DO
VOUT
Unweighted, 100 Hz to
8 kHz BW, mono
Unweighted, 100 Hz to
22 kHz BW, mono
−Vbat
V
OUT
0
−
2
V
Audio performance will be degraded below 1.05 V.
Measured with a = 12 dB input signal.
Input stage delay is inversely proportional to sampling frequency.
Max voltage should be limited to 2.2 V peak regardless of VDDC. Protection diodes will be enabled above this voltage.
http://onsemi.com
4
BELASIGNA 250
Table 2. ELECTRICAL SPECIFICATIONS
(continued)
Description
ANALOG OUTPUT STAGE
Attenuator gain tolerance
Output impedance
ATG
R
OUT
Input is –6 dB re: full scale @
1 kHz (all preamplifier gains)
Attenuator settings:
0 dB
12 dB
15 dB
18 dB
21 dB
24 dB
27 dB
30 dB
0 dB attenuation
Unweighted, 100 Hz to
8 kHz BW, mono
Unweighted, 100 Hz to
22 kHz BW, mono
−1
−
1
dB
√
Symbol
Conditions
Min
Typ
Max
Units
Screened
1
9
7
4
3
2
1
1
−
85
−
2
13
10
8
6
4
3
2
33
87
−70
5
17
14
12
9
7
6
5
40
−
−67
kW
√
Output noise
Output dynamic range
Output THD+N
OUT
N
OUT
DR
OUT
THDN
mV
dB
dB
ANTI−ALIASING FILTERS (Input and Output)
Preamplifier filter cut−off frequency
Digital anti−aliasing filter cut−off
frequency
Analog output cut−off frequency
25 kHz
12 kHz (only output filter)
Passband flatness
Stopband attenuation
LOW−SPEED A/D
Input voltage
INL
DNL
Maximum variation over
temperature (0_C to 50_C)
Sampling frequency
Channel sampling frequency
DIGITAL PADS
Voltage level for high input
V
IH
VDDC
* 0.8
−0.3
−
−
VDDC = 1.0 V
VDDC = 1.25 V
VDDC = 2.0 V
3.
4.
5.
6.
−
−
−
−
VDDC
+ 0.5
(Note 6)
VDDC
* 0.2
−
−
−
−
−
V
All channels sequentially
8 channels
Peak input voltage
From GND to 2*VREG
From GND to 2*VREG
0
−
−
−
−
−
−
−
−
−
12.8
1.6
2.0
10
2
5
−
−
V
LSB
LSB
LSB
kHz
kHz
√
60 kHz (12 kHz cut−off)
Preamp not bypassed
−
−
15
9
−1
−
25
f
s
/2
25
12
−
60
−
−
35
15
1
−
kHz
kHz
dB
dB
kHz
Voltage level for low input
Input capacitance for digital pads
Pull−up resistance for digital input
pads
Pull−down resistance to VDDC for
digital input pads
V
IL
C
IN
R
UP_IN
R
DOWN_IN
−
2
260
430
260
140
V
pF
kW
kW
kW
kW
√
√
Audio performance will be degraded below 1.05 V.
Measured with a = 12 dB input signal.
Input stage delay is inversely proportional to sampling frequency.
Max voltage should be limited to 2.2 V peak regardless of VDDC. Protection diodes will be enabled above this voltage.
http://onsemi.com
5
Analog electronics
京公网安备 11010802033920号
EEWORLD
