PI6LC4833
Clock Generator for Power PC
Features
ÎÎ
2.5/3.3V supply voltage
ÎÎ
HCSL 100/125/200/250MHz outputs with OE
4
ÎÎ
LVCMOS 33/50/66/100MHz selectable outputs
2
ÎÎ
LVCMOS 25MHz or 125MHz outputs
5
ÎÎ
LVPECL 312.5MHz, 156.25MHz or 125MHz output
1
ÎÎ
CMOS 156.25MHz or 125MHz output
1
ÎÎ
LVPECL 125MHz or 25MHz output
1
ÎÎ
25MHz crystal or differential input
ÎÎ
0.5ps (typ) RMS integrated phase noise design at 3.3V
Description
The PI6LC4833 implements Pericom's advanced LC VCO tech-
nology and is specifically designed for Power PC network pro-
cessor (Freescale MPC8548, MPC8572, AMCC 460, AMI732).
This high performance device is optimized to generate CPU core/
PCI clock, high performance PCIe Gen1/2 Clock, SRIO, Gigabit
Ethernet’s MAC and PHY clock. All outputs are generated from
25MHz external clock input or crystal.
Application
ÎÎ
Router/Switch
ÎÎ
OLT, BSC, WLAN, Wireless gateway
ÎÎ
Wireless
operation
operation
ÎÎ
1.0ps (typ) RMS integrated phase noise design at 2.5V
ÎÎ
PLL Bypass mode for test
ÎÎ
Industrial Temperature -40°C to 85°C
ÎÎ
TQFN - 56 package
Pin Configuration (56-Pin TQFN)
VDDA1
GND
QA2+
QA2-
VCCA
QA0-
VCCA
QA3+
QA1+
QA1-
QA0+
QA3-
IREF
GND
OC-B
FB0
FB1
VCCB
QB0
QB1
VDD_OSC
X1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
56 55 54 53 52 51 50 49 48 47 46 45 44 43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
FA1
FA0
OC-A
SS1
SS0
PLL_BYPS
VSEL_33
VCCC1
QC1
VCCC0
QC0-
QC0+
SEL_FREQ3
QC-C
GND
X2
IN+
IN-
IN_Sel
OC-R
Sel_Freq2
15 16 17 18 19 20 21 22 23 24 25 26 27 28
VccR
VccD
QD2
VCCR
Qref2
VDDA2
GND
Qref0
Qref1
VDD_PLL2
QD0+
QD0-
Sel_Freq1
QD1
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P-0.1
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Clock Generator for Power PC
Block Diagram
PI6LC4833
F
B0
F
B1
SS1
SS0
I
ref
F
A1
F
A0
Q
A3+
Q
A3-
Q
A2+
Q
A2-
Q
A1+
Q
A1-
Q
A0+
Q
A0-
PLL-BYPS
Q
B0
/Q
B1
PLL-BYPS
Q
CO+
Q
CO-
Q
C1
IN_Sel
Divider
X1
X2
IN+
IN-
Diff
OSC
MUX
LC
PLL2
Divider
S
Sel-Freq3
PLL_BYPS
OC_A
OC_B
OC_C
OC_R
VSEL_33
PLL-BYPS
Ring
PLL1
Divider
Divider
IN1
IN2
S
IN1
IN2
PLL-BYPS
Q
DO+
Q
DO-
Q
D1
Q
D2
Qref0
Qref1
Qref2
S
PLL-BYPS
Sel-Freq1 Sel-Freq2
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Clock Generator for Power PC
Pinout Table
Pin Number
44, 45, 47, 48,
50, 51, 53, 54
5, 6
8
9
10, 11
12
PI6LC4833
Pin Name
I/O Type
Description
100/125/200/250MHz HCSL Outputs
33/50/66/100MHz LVCMOS Outputs
Crystal Input Pin
Oscillator Output Pin
HCSL/LVPECL/LVDS Inputs
Low: X1 and X2 are selected.
High: IN+ and IN- are selected.
The pin has an internal pull-up resistor of 100kΩ.
Low: Output buffers are switched to the PLL.
Q
A0+
, Q
A0-
, Q
A1+
, Q
A1-
,
Output
Q
A2+
, Q
A2-
, Q
A3+
, Q
A3-
Q
B0
, Q
B1
X1
X2
IN+, IN-
IN_Sel
Output
Input
Output
Input
Input
37
PLL_BYPS
Input
High: Output buffers are switched to the input mux.
The pin has an internal pull-down resistor of 100kΩ.
Low: Outputs are enabled.
High: High impedance mode is selected.
The pin has an internal pull-down resistor of 100kΩ.
Power for crystal OSC core
Power for LC PLL2
Power for output buffers (Q
A
, Q
B
, Q
C
, Q
D
, Q
ref
)
Power for Ring PLL1
Ground includes external paddle (EPAD).
125MHz/156.25MHz/312.5MHz LVCMOS and LVPECL
25MHz or 125MHz LVCMOS, or LVPECL (Q
D0+
/Q
D0-
)
Q
A
Bank Output Frequency Selection (see function table). This pin has a
built-in pull-down resistor of 100kΩ.
Q
B
Bank Output Frequency Selection (see function table). This pin has a
built-in pull-up resistor of 100kΩ.
Low: Q
D
25MHz Output
High: Q
D
125MHz Output
This pin has a built-in pull-up resistor of 100kΩ.
Power for PLL2 Core
Low: Q
ref
25MHz Output
High: 125MHz Output
This pin has a built-in pull-down resistor of 100kΩ.
40, 1, 29, 13
7
21
OC_A, OC_B, OC_C,
Input
OC_R
V
DD_OSC
V
DDA2
Power
Power
Power
Power
Power
Output
Output
Input
Input
46, 52, 4, 33, 35, V
ccA
, V
ccB
, V
ccC0
, V
ccC1
28, 15, 19
V
ccD
, V
ccR
56
20, 49, 55
34, 31, 32
16, 17, 18, 23,
24, 26, 27
42, 41
3, 2
V
DD
A1
GND
Q
C1
, Q
C0+
/ Q
C0-
Q
ref0
, Q
ref1
, Q
ref2
,
Q
D0+
/Q
D0-
. Q
D1
, Q
D2
F
A1
, FA0
F
B1
, F
B0
25
22
14
Sel_Freq1
V
DD
_PLL2
Sel_Freq2
Input
Power
Input
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P-0.1
06/14/11
Clock Generator for Power PC
PI6LC4833
Pin Number
Pin Name
I/O Type
Description
Low: Q
C
156.25MHz Output
High: 125MHz Output
30
Sel_Freq3
Input
Floating: Output 312.5MHz (Q
C1
is HiZ if floating)
This pin has a built-in pull-up resistor of 150kΩ and pull-down resistor
of 100kΩ.
39, 38
43
36
SS1, SS0
I
REF
VSEL_33
Input
Input
Input
Spread Selection Pin for Q
A
and Q
B
This pin has a built-in pull-up resistor of 100kΩ (see function table).
External resistor connection for internal current reference
Low: 2.5V mode, High: 3.3V mode
This pin has a built-in pull_up resistor of 100kΩ
Function Table
Output
Q
A0+/-
, Q
A1+/-
, Q
A2+/-
,
Q
A3+/-
Q
B1
, Q
B0
Q
C0+/-
Q
C1
Q
D0+/-
Q
D2
, Q
D1
Q
ref2
, Q
ref1
, Q
ref0
Buffer
HCSL x4
CMOS x2
LVPECL x1
CMOS x1
LVPECL x1
CMOS x2
CMOS x3
Frequency (MHz)
100, 125, 200, 250
33.3333, 50, 66.6667, 100
125, 156.25, 312.5
125, 156.25, HiZ
25, 125
25, 125
25, 125
Selection Pin
F
A1
, F
A0
F
B1
, F
B0
Sel_Freq3
Sel_Freq1
Sel_Freq2
F
B1
0
0
1
1
F
B0
0
1
0
1
Q
B0
33.33MHz
66.66MHz
100MHz
50MHz
Q
B1
33.33MHz
66.66MHz
100MHz
50MHz
Output
LVCMOS
LVCMOS
LVCMOS
LVCMOS
F
A1
0
0
1
1
F
A0
0
1
0
1
Q
A0+
/Q
A0-
100MHz
125MHz
200MHz
250MHz
Q
A1+
/Q
A1-
100MHz
125MHz
200MHz
250MHz
Q
A2+
/Q
A2-
100MHz
125MHz
200MHz
250MHz
Q
A3+
/Q
A3-
100MHz
125MHz
200MHz
250MHz
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P-0.1
06/14/11
Clock Generator for Power PC
PI6LC4833
Sel_Freq3
0
1
NC
Q
Cx
Q
Cx
Q
Cx
Q
C0
Q
C1
Output_Freq
156.25MHz
125MHz
312.5MHz
HiZ
Sel_Freq1
0
1
Q
D0+
, Q
D0-
LVPECL
LVPECL
Q
D2,
Q
D1
LVCMOS
LVCMOS
Output_Freq
25MHz
125MHz
Sel_Freq2
0
1
Q
ref2,
Q
ref1
, Q
ref0
LVCMOS
LVCMOS
Output_Freq
25MHz
125MHz
SS1
0
0
1
1
SS0
0
1
0
1
Spread %
+/- 0.25
-0.5
-0.75
No spread
Note: The SS1 and SS0 pins control the spread ratio of both
Q
A
and
Q
B.
All trademarks are property of their respective owners.
11-0074
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P-0.1
06/14/11
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