1
FINAL
MACH 1 & 2 FAMILIES
COM’L: -7/10/12/15
IND: -10/12/14/18
MACH211SP-7/10/12/15
High-Performance EE CMOS
In-System Programmable Logic
DISTINCTIVE CHARACTERISTICS
x
JTAG-Compatible, 5-V in-system programming
x
44 Pins in PLCC and TQFP
x
64 Macrocells
x
7.5 ns t
PD
Commercial, 10 ns t
PD
Industrial
x
133 MHz f
CNT
x
32 I/Os; 2 dedicated inputs/clocks
x
64 Flip-flops; 2 clock choices
x
4 “PALCE26V16” blocks with buried macrocells
x
Speed Locking™ for guaranteed fixed timing
x
Bus-Friendly™ Inputs and I/Os
x
Peripheral Component Interconnect (PCI) compliant (-7/-10/-12)
x
Programmable power-down mode
MACH 1 & 2 Families
IN-SYSTEM PROGRAMMING
In-system programming allows the MACH211SP to be programmed while soldered onto a system
board. Programming the MACH211SP in-system yields numerous benefits at all stages of
development: prototyping, manufacturing, and in the field. Since insertion into a programmer isn’t
needed, multiple handling steps and the resulting bent leads are eliminated. The design can be
modified in-system for design changes and debugging while prototyping, programming boards in
production, and field upgrades.
The MACH211SP offers advantages with in-system programming. MACH
®
devices have
extensive routing resources for pin-out retention; design changes resulting in pin-out changes
for many non-Vantis CPLDs cancel the advantages of in-system programming. The MACH211SP
can be deployed in any JTAG (IEEE 1149.1) compliant chain.
GENERAL DESCRIPTION
The MACH211SP is a member of Vantis’ high-performance EE CMOS MACH 1 & 2 families. This
device has approximately six times the logic macrocell capability of the popular PALCE22V10
without loss of speed.
The MACH211SP consists of four PAL
®
blocks interconnected by a programmable switch matrix.
The four PAL blocks are essentially “PALCE26V16” structures complete with product-term arrays
and programmable macrocells, which can be programmed as high speed or low power, and buried
macrocells. The switch matrix connects the PAL blocks to each other and to all input pins,
Publication#
20405
Amendment/0
Rev:
C
Issue Date:
August 1997
1
V A N T I S
providing a high degree of connectivity between the fully-connected PAL blocks. This allows
designs to be placed and routed efficiently.
The MACH211SP has two kinds of macrocell: output and buried. The MACH211SP output
macrocell provides registered, latched, or combinatorial outputs with programmable polarity. If a
registered configuration is chosen, the register can be configured as D-type or T-type to help
reduce the number of product terms. The register type decision can be made by the designer or
by the software. All output macrocells can be connected to an I/O cell. If a buried macrocell is
desired, the internal feedback path from the macrocell can be used, which frees up the I/O pin
for use as an input.
The MACH211SP has dedicated buried macrocells which, in addition to the capabilities of the
output macrocell, also provide input registers or latches for use in synchronizing signals and
reducing setup time requirements.
The MACH211SP is an enhanced version of the MACH211, adding the JTAG-compatible in-system
programming feature.
Vantis offers software design support for MACH devices through its own development system and
device fitters integrated into third-party CAE tools. Platform support extends across PCs, Sun and
HP workstations under advanced operating systems such as Windows 3.1, Windows 95 and NT,
SunOS and Solaris, and HPUX.
MACHXL
®
software is a complete development system for the PC, supporting Vantis' MACH
devices. It supports design entry with Boolean and behavioral syntax, state machine syntax and
truth tables. Functional simulation and static timing analysis are also included in this easy-to-use
system. This development system includes high-performance device fitters for all MACH devices.
The same fitter technology included in MACHXL software is seamlessly incorporated into third-party
tools from leading CAE vendors such as Synario, Viewlogic, Mentor Graphics, Cadence and MINC.
Interface kits and MACHXL configurations are also available to support design entry and verification
with other leading vendors such as Synopsys, Exemplar, OrCAD, Synplicity and Model Technology.
These MACHXL configurations and interfaces accept EDIF 2.0.0 netlists, generate JEDEC files for
MACH devices, and create industry-standard SDF, VITAL-compliant VHDL and Verilog output files for
design simulation.
Vantis offers in-system programming support for MACH devices through its MACHPRO
®
software
enabling MACH device programmability through JTAG compliant ports and easy-to-use PC
interface. Additionally, MACHPRO generated vectors work seamlessly with HP3070, GenRad and
Teradyne testers to program MACH devices or test them for connectivity.
All MACH devices are supported by industry standard programmers available from a number of
vendors. These programmer vendors include Advin Systems, BP Microsystems, Data I/O
Corporation, Hi-Lo Systems, SMS GmbH, Stag House, and System General.
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MACH211SP-7/10/12/15
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