Philips Semiconductors
Product data
Low voltage 1:10 differential
ECL/PECL/HSTL clock driver
PCK111
FEATURES
•
85 ps part-to-part skew typical
•
20 ps output-to-output skew typical
•
Differential design
•
V
BB
output
•
Low voltage V
EE
range of –2.25 V to –3.8 V for ECL
•
Low voltage V
CC
range of +2.375 V to +3.8 V for PECL
•
75 kΩ input pull-down resistors
•
ECL/PECL outputs
•
Form, fit, and function compatible with MC100EP111
DESCRIPTION
The PCK111 is a low skew 1-to-10 differential driver, designed with
clock distribution in mind. It accepts two clock sources into an input
multiplexer. The PECL input signals can be either differential or
single-ended if the V
BB
output is used. The selected signal is fanned
out to 10 identical differential outputs.
The PCK111 is specifically designed, modeled and produced with
low skew as the key goal. Optimal design and layout serve to
minimize gate-to-gate skew within a device, and empirical modeling
is used to determine process control limits that ensure consistent
t
PD
distributions from lot to lot. The net result is a dependable,
guaranteed low skew device.
To ensure that the tight skew specification is met, it is necessary that
both sides of the differential output are terminated into 50
Ω,
even if
only one side is being used. In most applications, all ten differential
pairs will be used, and therefore terminated. In the case where fewer
than ten pairs are used, it is necessary to terminate at least the
output pairs on the same package side as the pair(s) being used on
that side, in order to maintain minimum skew. Failure to do this will
result in small degradations of propagation delay (on the order of
10–20 ps) of the output(s) being used, which, while not being
catastrophic to most designs, will mean a loss of skew margin.
The PCK111 can be used for high performance clock distribution in
+3.3 V or +2.5 V systems. Designers can take advantage of the
PCK111’s performance to distribute low skew clocks across the
backplane or the board. In a PECL environment, series or Thevenin
line terminations are typically used as they require no additional
power supplies.
The PCK111 may be driven single-endedly utilizing the V
BB
bias
output with the CLK0 input. If a single-ended signal is to be used,
the V
BB
pin should be connected to the CLK0 input and bypassed to
ground via a 0.01
µF
capacitor. The V
BB
output can only source/sink
0.2 mA, therefore, it should be used as a switching reference for the
PCK111 only. Part-to-part skew specifications are not guaranteed
when driving the PCK111 single-endedly.
PINNING
Pin configurations
V
CCO
V
CCO
25
Q0
Q0
Q1
Q1
Q2
27
32
31
30
29
28
V
CC
CLK_SEL
CLK0
CLK0
V
BB
CLK1
CLK1
V
EE
1
2
3
4
5
6
7
8
26
Q2
24 Q3
23 Q3
22 Q4
21 Q4
PCK111BD
20 Q5
19 Q5
18 Q6
17 Q6
Q9 10
Q8 12
Q8 13
Q7 14
Q7 15
V
CCO
16
V
CCO
Q9 11
9
SW00907
Figure 1. LQFP32 pin configuration
V
CCO
32
31
30
29
28
27
26
25
V
CCO
Q0
Q0
Q1
Q1
Q2
Q2
V
CC
CLK_SEL
CLK0
CLK0
V
BB
CLK1
CLK1
V
EE
1
2
3
4
5
6
7
8
10
12
13
14
15
16
11
9
24
23
22
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
PCK111BS
(TOP VIEW)
21
20
19
18
17
Q9
Q9
Q8
Q8
Q7
V
CCO
Q7
Figure 2. HVQFN32 pin configuration
ORDERING INFORMATION
Type number
n mber
PCK111BD
PCK111BS
Package
Name
LQFP32
HVQFN32
Description
plastic low profile quad flat package; 32 leads; body 7
×
7
×
1.4 mm
plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5
×
5
×
0.85 mm
Version
SOT358-1
SOT617-1
Temperature
p
range
–40
°C
to +85
°C
–40
°C
to +85
°C
2004 Apr 23
2
V
CCO
SW02236
Philips Semiconductors
Product data
Low voltage 1:10 differential
ECL/PECL/HSTL clock driver
PCK111
Pin description
SYMBOL
V
CC
CLK_SEL
CLK0, CLK0
V
BB
CLK1, CLK1
V
EE
V
CCO
Q0–Q9
PIN
1
2
3, 4
5
6, 7
8
9, 16, 25, 32
31, 29, 27, 24,
22, 20, 18, 15,
13, 11
30, 28, 26, 23,
21, 19, 17, 14,
12, 10
DESCRIPTION
Supply voltage
Active CMOS clock select input
Differential ECL/PECL/HSTL
input pair
Reference voltage output
Differential ECL/PECL/HSTL
input pair
Ground
Output drive power supply
voltage
Differential PECL outputs
LOGIC SYMBOL
CLK0
CLK0
CLK1
CLK1
1
0
10
Q0:9
Q0:9
V
BB
CLK_SEL
SW00908
Figure 3. Logic symbol
FUNCTION TABLE
CLK_SEL
Active input
CLK0, CLK0
CLK1, CLK1
0
1
Q0–Q9
Differential PECL outputs
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.
SYMBOL
V
CC
ESDHBM
ESDMM
ESDCDM
Supply voltage
Electrostatic discharge (Human Body Model; 1.5 kΩ, 100 pF)
Electrostatic discharge (Machine Model; 0 kΩ, 200 pF)
Electrostatic discharge (Charge Device Model)
PARAMETER
LIMITS
–0.5 to +4.6
>1.75
>200
>1000
UNIT
V
kV
V
V
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
IR
V
DIFF
T
amb
Supply voltage
Receiver input voltage
Input differential voltage
1
Operating ambient temperature range in free air
V
(CLKinN)–
V
(CLKin)
PARAMETER
CONDITIONS
MIN
2.25
V
EE
—
–40
MAX
3.8
V
CC
1.00
+85
UNIT
V
V
V
°C
NOTE:
1. To idle an unused differential clock input, connect one input terminal (e.g. CLK1) to V
BB
and leave its complimentary input terminal
(e.g. CLK1) open-circuit, in which case CLK1 will default LOW by its internal pull-down reistor. Inputs should not be shorted to ground or
V
CC.
2004 Apr 23
3
Philips Semiconductors
Product data
Low voltage 1:10 differential
ECL/PECL/HSTL clock driver
PCK111
DC ELECTRICAL CHARACTERISTICS
V
CC
= 0 V, V
EE
= –2.25 to –3.80 V
SYMBOL
I
EE
I
CC
I
IN
V
BB
V
IH
V
IL
V
PP
V
CMR
V
OH
V
OL
V
OUTpp
PARAMETER
Internal supply current
Output and internal supply
current
Input current
Internal bias voltage
In ut
Input HIGH voltage
In ut
Input LOW voltage
Input amplitude
Common mode voltage
Output HIGH voltage
Output LOW voltage
Differential output swing
Single ended
CLK_SEL
Single ended
CLK_SEL
Difference of input = V
IH
–
V
IL
(Note 1)
Cross point of input =
average (V
IH
, V
IL
)
I
OH
= –30 mA
I
OL
= –5 mA
CONDITION
Absolute value of current
All outputs terminated 50
Ω
to V
CC
= –2.0 V
Includes pullup/pulldown
resistors
–40
°C
MIN
45
270
—
–1.38
–1.165
0.2V
EE
–1.810
V
EE
0.5
V
EE
+
1.0
–1.3
–1.85
350
–40
°C
MAX
85
360
150
–1.23
–0.880
V
CC
–1.475
0.8V
EE
1.3
–0.3
–0.95
–1.4
—
25
°C
MIN
60
290
—
–1.38
–1.165
0.2V
EE
–1.810
V
EE
0.5
V
EE
+
1.0
—
—
—
25
°C
MAX
95
380
150
–1.23
–0.880
V
CC
–1.475
0.8V
EE
1.3
–0.3
—
—
—
85
°C
MIN
65
300
—
–1.38
–1.165
0.2V
EE
–1.810
V
EE
0.5
V
EE
+
1.0
–1.2
–1.90
500
85
°C
MAX
105
380
150
–1.23
–0.880
V
CC
–1.475
0.8V
EE
1.3
–0.3
0.90
–1.5
—
UNIT
mA
mA
µA
V
V
V
V
V
V
V
V
V
MV
NOTE:
1. V
PP
minimum and maximum required to maintain AC specifications. Actual device function will tolerate minimum V
PP
of 100 mV.
DC ELECTRICAL CHARACTERISTICS
V
CC
= V
CCO
= 2.25 to 3.80 V, V
EE
= 0 V
SYMBOL
I
EE
I
CC
I
IN
V
BB
PARAMETER
Internal supply current
Output and internal supply
current
Input current
Internal bias voltage
Single ended
CLK_SEL
V
IL
Input LOW voltage
g
Single ended
CLK_SEL
V
PP
V
CMR
V
IHCMR
V
x
V
OH
V
OL
V
OUTpp
Input amplitude
Common mode voltage
Input HIGH voltage
(HSTL)
Input crossover voltage
(HSTL)
Output HIGH voltage
Output LOW voltage
Differential output swing
Cross point of input =
average (V
IH
, V
IL
)
I
OH
= –30 mA
I
OL
= –5 mA
Difference of input =
V
IH
– V
IL
(Note 1)
Cross point of input =
average (V
IH
, V
IL
)
CONDITION
Absolute value of current
All outputs terminated
50
Ω
to V
CC
= –2.0 V
Includes pullup/pulldown
resistors
–40
°C
MIN
45
270
—
V
CC
–1.38
V
CC
–1.165
0.8V
CC
V
CC
–1.810
V
EE
0.5
1.0
1.2
0.68
V
CC
–1.30
V
CC
–1.85
350
–40
°C
MAX
85
360
150
V
CC
–1.23
V
CC
–0.880
V
CC
V
CC
–1.475
0.2V
CC
1.3
V
CC
–0.3
V
CC
0.9
V
CC
–0.95
V
CC
–1.40
—
25
°C
MIN
60
290
—
V
CC
–1.38
V
CC
–1.165
0.8V
CC
V
CC
–1.810
V
EE
0.5
1.0
1.2
0.68
—
—
—
25
°C
MAX
95
380
150
V
CC
–1.23
V
CC
–0.880
V
CC
V
CC
–1.475
0.2V
CC
1.3
V
CC
–0.3
V
CC
0.9
—
—
—
85
°C
MIN
65
300
—
V
CC
–1.38
V
CC
–1.165
0.8V
CC
V
CC
–1.810
V
EE
0.5
1.0
1.2
0.68
V
CC
–1.20
V
CC
–1.90
500
85
°C
MAX
105
380
150
V
CC
–1.23
V
CC
–0.880
V
CC
V
CC
–1.475
0.2V
CC
1.3
V
CC
–0.3
V
CC
0.9
V
CC
–0.90
V
CC
–1.50
—
UNIT
mA
mA
µA
V
V
V
V
V
V
V
V
V
V
V
MV
V
IH
Input HIGH voltage
g
NOTE:
1. V
PP
minimum and maximum required to maintain AC specifications. Actual device function will tolerate minimum V
PP
of 100 mV.
2004 Apr 23
4
Philips Semiconductors
Product data
Low voltage 1:10 differential
ECL/PECL/HSTL clock driver
PCK111
AC ELECTRICAL CHARACTERISTICS
V
CC
= 2.25 V to 3.80 V, V
EE
= 0 V, or V
CC
= 0 V, V
EE
= –2.25 V to –3.80 V
SYMBOL
PARAMETER
CONDITION
Nominal (single input
condition) V
PP
= 0.650 V,
V
CMR
= V
CC
– 0.800 V
(Note 1)
Note 1
Note 1
–40
°C
MIN
–40
°C
MAX
25
°C
MIN
25
°C
MAX
85
°C
MIN
85
°C
MAX
UNIT
t
PD
t
skew
t
skew
t
jitter
f
MAX
t
r
/t
f
Differential propagation
delay
Part-to-part skew
Output-to-output same part
skew
Cycle-to-cycle jitter
Maximum output frequency
Output rise/fall time at 20%
to 80%
350
500
380
530
450
590
ps
—
—
—
110
50
1
1500
—
—
—
—
110
50
1
1500
—
—
—
—
110
50
1
1500
ps
ps
ps
MHz
Functional to 1.5 GHz;
Timing specifications apply
to 1.0 GHZ
All outputs terminated 50
Ω
to V
CC
– 2.0 V
—
100
300
100
300
100
300
ps
NOTE:
1. For operation with 2.5 V supply, the output termination is 50
Ω
to V
EE
.
For operation with 3.3 V supply, the output termination is 50
Ω
to V
CC
– 2 V.
2004 Apr 23
5
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