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8752CYLF

Description
Clock Buffer 1-to-8 LVCMOS Clock Generator/Zero Delay
Categorysemiconductor    Analog mixed-signal IC   
File Size133KB,14 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
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8752CYLF Overview

Clock Buffer 1-to-8 LVCMOS Clock Generator/Zero Delay

8752CYLF Parametric

Parameter NameAttribute value
Product CategoryClock Buffer
ManufacturerIDT (Integrated Device Technology, Inc.)
RoHSDetails
Number of Outputs8 Output
Maximum Input Frequency240 MHz
Supply Voltage - Max3.465 V
Supply Voltage - Min3.135 V
Maximum Operating Temperature+ 70 C
Minimum Operating Temperature0 C
Mounting StyleSMD/SMT
Package / CaseTQFP-32
PackagingTray
Height1.4 mm
Length7 mm
Moisture SensitiveYes
Operating Supply Current105 mA
Factory Pack Quantity250
Width7 mm
Unit Weight0.002568 oz
ICS8752
L
OW
S
KEW
, 1-
TO
-8
LVCMOS C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS8752 is a low voltage, low skew LVCMOS clock
generator. With output frequencies up to 240MHz, the
ICS8752 is targeted for high performance clock applcations.
Along with a fully integrated PLL, the ICS8752 contains
frequency configurable outputs and an external feedback
input for regenerating clocks with “zero delay”.
Dual clock inputs, CLK0 and CLK1, support redundant clock
applications. The CLK_SEL input determines which refer-
ence clock is used. The output divider values of Bank A and
B are controlled by the DIV_SELA0:1, and DIV_SELB0:1,
respectively.
For test and system debug purposes, the PLL_SEL input
allows the PLL to be bypassed. When HIGH, the MR/nOE
input resets the internal dividers and forces the outputs to
the high impedance state.
The low impedance LVCMOS outputs of the ICS8752 are
designed to drive terminated transmission lines. The
effective fanout of each output can be doubled by
utilizing the ability of each output to drive two series
terminated transmission lines.
F
EATURES
Fully integrated PLL
Eight LVCMOS outputs, 7Ω typical output impedance
Selectable LVCMOS CLK0 or CLK1 inputs for
redundant clock applications
Input/Output frequency range: 18.33MHz to 240MHz
at V
CC
= 3.3V ± 5%
VCO range: 220MHz to 480MHz
External feedback for “zero delay” clock regeneration
Cycle-to-cycle jitter: 75ps (maximum),
(all outputs are the same frequency)
Output skew: 100ps (maximum)
Bank skew: 55ps (maximum)
Full 3.3V or 2.5V supply voltage
0°C to 70°C ambient operating temperature
Available in both standard and lead-free RoHS-compliant
packages
B
LOCK
D
IAGRAM
PLL_SEL
PLL
FB_IN
CLK0
0
CLK1
1
CLK_SEL
DIV_SELA1
DIV_SELA0
00
01
10
11
PHASE
DETECTOR
VCO
1
0
÷2
÷4
÷6
÷8
÷12
00
01
10
11
P
IN
A
SSIGNMENT
PLL_SEL
GND
GND
V
DDO
QB3
QB2
V
DD
nc
32 31 30 29 28 27 26 25
QA0
QA1
QA2
QA3
DIV_SELB0
DIV_SELB1
DIV_SELA0
DIV_SELA1
MR/nOE
CLK0
QB0
QB1
QB2
QB3
CLK_SEL
V
DDA
V
DD
CLK1
GND
QA0
QA1
V
DDO
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
24
23
22
GND
QB1
QB0
V
DDO
V
DDO
QA3
QA2
GND
ICS8752
21
20
19
18
17
GND
FB_IN
DIV_SELB1
DIV_SELB0
MR/nOE
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y package
Top View
8752CY
www.idt.com
1
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