AT89C51RC-24JU datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> AT89C51RC-24JU

AT89C51RC-24JU: DescriptionLogic Gates Quad 2-In Pos NAND; CategoryThe embedded processor and controller Microcontrollers and processors; File Size355KB，37 Pages; ManufacturerAtmel (Microchip); Environmental Compliance

Download Datasheet Parametric Compare View All

AT89C51RC-24JU Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	AT89C51RC-24JU	-	-	View	Buy Now

AT89C51RC-24JU Overview

Logic Gates Quad 2-In Pos NAND

AT89C51RC-24JU Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	LPCC
package instruction	QCCJ, LDCC44,.7SQ
Contacts	44
Reach Compliance Code	unknown
ECCN code	3A991.A.2
Has ADC	NO
Address bus width	16
bit size	8
CPU series	8051
maximum clock frequency	24 MHz
DAC channel	NO
DMA channel	NO
External data bus width	8
JESD-30 code	S-PQCC-J44
JESD-609 code	e3
length	16.5862 mm
Humidity sensitivity level	2
Number of I/O lines	32
Number of terminals	44
On-chip program ROM width	8
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
PWM channel	NO
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC44,.7SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	245
power supply	5 V
Certification status	Not Qualified
RAM (bytes)	512
rom(word)	32768
ROM programmability	FLASH
Maximum seat height	4.57 mm
speed	24 MHz
Maximum slew rate	25 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	4 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	16.5862 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER
Base Number Matches	1

Preview

Download Datasheet

View All

Features

•

Compatible with MCS

-51 Products

32K Bytes of Reprogrammable Flash Memory

Endurance: 10,000 Write/Erase Cycles

4V to 5.5V Operating Range

Fully Static Operation: 0 Hz to 33 MHz

Three-level Program Memory Lock

512 x 8-bit Internal RAM

32 Programmable I/O Lines

Three 16-bit Timer/Counters

Eight Interrupt Sources

Programmable Serial Channel

Low-power Idle and Power-down Modes

Interrupt Recovery from Power-down Mode

Hardware Watchdog Timer

Dual Data Pointer

Power-off Flag

Green (Pb/Halide-free) Packaging Option

8-bit

Microcontroller

with 32K Bytes

Flash

AT89C51RC

1. Description

The AT89C51RC is a low-power, high-performance CMOS 8-bit microcontroller with

32K bytes of Flash programmable read-only memory and 512 bytes of RAM. The

device is manufactured using Atmel’s high-density nonvolatile memory technology

and is compatible with the industry-standard 80C51 and 80C52 instruction set and

pinout. The on-chip Flash allows the program memory to be user programmed by a

conventional nonvolatile memory programmer. A total of 512 bytes of internal RAM

are available in the AT89C51RC. The 256-byte expanded internal RAM is accessed

via MOVX instructions after clearing bit 1 in the SFR located at address 8EH. The

other 256-byte RAM segment is accessed the same way as the Atmel AT89-series

and other 8052-compatible products. By combining a versatile 8-bit CPU with Flash

on a monolithic chip, the Atmel AT89C51RC is a powerful microcomputer which pro-

vides a highly-flexible and cost-effective solution to many embedded control

applications.

The AT89C51RC provides the following standard features: 32K bytes of Flash, 512

bytes of RAM, 32 I/O lines, three 16-bit timer/counters, a six-vector two-level interrupt

architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition,

the AT89C51RC is designed with static logic for operation down to zero frequency

and supports two software selectable power saving modes. The Idle Mode stops the

CPU while allowing the RAM, timer/counters, serial port, and interrupt system to con-

tinue functioning. The Power-down mode saves the RAM contents but freezes the

oscillator, disabling all other chip functions until the next external interrupt or hardware

reset.

1920D–MICRO–6/08

4. Pin Description

4.1

VCC

Supply voltage.

4.2

GND

Ground.

4.3

Port 0

Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL

inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs.

Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses

to external program and data memory. In this mode, P0 has internal pull-ups.

Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur-

ing program verification.

External pull-ups are required during program verification.

4.4

Port 1

Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can

sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the inter-

nal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low

will source current (I

) because of the internal pull-ups.

In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input

(P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the follow-

ing table.

Port 1 also receives the low-order address bytes during Flash programming and verification.

Port Pin

P1.0

P1.1

Alternate Functions

T2 (external count input to Timer/Counter 2), clock-out

T2EX (Timer/Counter 2 capture/reload trigger and direction control)

4.5

Port 2

Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can

sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the inter-

nal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low

will source current (I

) because of the internal pull-ups.

Port 2 emits the high-order address byte during fetches from external program memory and dur-

ing accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this

application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external

data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special

Function Register.

Port 2 also receives the high-order address bits and some control signals during Flash program-

ming and verification.

AT89C51RC

1920D–MICRO–6/08

AT89C51RC

4.6

Port 3

Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can

sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the inter-

nal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low

will source current (I

) because of the pull-ups.

Port 3 receives some control signals for Flash programming and verification.

Port 3 also serves the functions of various special features of the AT89C51RC, as shown in the

following table.

Port Pin

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

Alternate Functions

RXD (serial input port)

TXD (serial output port)

INT0 (external interrupt 0)

INT1 (external interrupt 1)

T0 (timer 0 external input)

T1 (timer 1 external input)

WR (external data memory write strobe)

RD (external data memory read strobe)

4.7

RST

Reset input. A high on this pin for two machine cycles while the oscillator is running resets the

device. This pin drives High for 98 oscillator periods after the Watchdog times out. The DISRTO

bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit

DISRTO, the RESET HIGH out feature is enabled.

4.8

ALE/PROG

Address Latch Enable is an output pulse for latching the low byte of the address during

accesses to external memory. This pin is also the program pulse input (PROG) during Flash

programming.

In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be

used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped dur-

ing each access to external data memory.

If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set,

ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high.

Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.

4.9

PSEN

Program Store Enable is the read strobe to external program memory.

When the AT89C51RC is executing code from external program memory, PSEN is activated

twice each machine cycle, except that two PSEN activations are skipped during each access to

external data memory.

1920D–MICRO–6/08

AT89C51RC-24JU Related Products

	AT89C51RC-24JU	AT89C51RC-24PU
Description	Logic Gates Quad 2-In Pos NAND	Aluminum Organic Polymer Capacitors 6.3volts 560uF 20%
Is it lead-free?	Lead free	Lead free
Is it Rohs certified?	conform to	conform to
Parts packaging code	LPCC	DIP
package instruction	QCCJ, LDCC44,.7SQ	DIP, DIP40,.6
Contacts	44	40
Reach Compliance Code	unknown	unknown
ECCN code	3A991.A.2	3A991.A.2
Has ADC	NO	NO
Address bus width	16	16
bit size	8	8
CPU series	8051	8051
maximum clock frequency	24 MHz	24 MHz
DAC channel	NO	NO
DMA channel	NO	NO
External data bus width	8	8
JESD-30 code	S-PQCC-J44	R-PDIP-T40
JESD-609 code	e3	e3
length	16.5862 mm	52.324 mm
Humidity sensitivity level	2	1
Number of I/O lines	32	32
Number of terminals	44	40
On-chip program ROM width	8	8
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
PWM channel	NO	NO
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QCCJ	DIP
Encapsulate equivalent code	LDCC44,.7SQ	DIP40,.6
Package shape	SQUARE	RECTANGULAR
Package form	CHIP CARRIER	IN-LINE
Peak Reflow Temperature (Celsius)	245	245
power supply	5 V	5 V
Certification status	Not Qualified	Not Qualified
RAM (bytes)	512	512
rom(word)	32768	32768
ROM programmability	FLASH	FLASH
Maximum seat height	4.57 mm	4.826 mm
speed	24 MHz	24 MHz
Maximum slew rate	25 mA	25 mA
Maximum supply voltage	5.5 V	5.5 V
Minimum supply voltage	4 V	4 V
Nominal supply voltage	5 V	5 V
surface mount	YES	NO
technology	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	Matte Tin (Sn)	Matte Tin (Sn)
Terminal form	J BEND	THROUGH-HOLE
Terminal pitch	1.27 mm	2.54 mm
Terminal location	QUAD	DUAL
Maximum time at peak reflow temperature	40	NOT SPECIFIED
width	16.5862 mm	15.24 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER	MICROCONTROLLER
Base Number Matches	1	1

Recommended Resources

Single-phase full-wave controllable rectifier circuit Single-phase bridge half-controlled rectifier circuit

Capacitor low voltage centralized compensation circuit

megaphone circuit

555 touch bistable controller circuit

VMOS tube switching regulated power supply application circuit 2

Wire cutting machine tool control circuit

[Raspberry Pi 3B+ Review] MicroPython and Python: [i=s]This post was last edited by icefire2012 on 2018-9-16 20:53[/i] According to the test plan, micropython needs to be ported to the Raspberry Pi to control hardware. I downloaded the source code of...; icefire2012 MCU

C implementation of FFT operation on 28035: Implement FFT calculation on 28035 in C. What are the specific differences between using the trigonometric functions in the C library math.h and the trigonometric functions in IQmathLib.h for calculat...; l0700830216 Microcontroller MCU

【SINA31s Review】NO.5 The First Driver: Busy[/font][/align][align=left][font=宋体]I haven't updated for a long time,[/font]SINA31s[font=宋体]is beginning to gather dust[/font][/align][align=left][font=宋体]I wrote a simple character device driver...; ljj3166 Embedded System

Multi-channel voice control switching circuit (paid part-time job): Design and development requirements: There are 8 voice communication work units, and each work unit is connected by wire. Each work unit is equipped with a headset microphone and a control button to s...; longkey Analog electronics

Who has done testability design and test sequence analysis?: How to optimize the reserved test points during circuit design?...; wilgachen FPGA/CPLD

NIOS II Video Tutorial: ...; number007cool FPGA/CPLD

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components