Data Sheet
FEATURES
Dual, 14-Bit, 1230 MSPS,
TxDAC+ Digital-to-Analog Converter
AD9121
The AD9121 TxDAC+® includes features optimized for direct
conversion transmit applications, including complex digital mod-
ulation, and gain and offset compensation. The DAC outputs
are optimized to interface seamlessly with analog quadrature
modulators, such as the
ADL537x
F-MOD series from Analog
Devices, Inc. A 4-wire serial port interface provides for program-
ming/readback of many internal parameters. Full-scale output
current can be programmed over a range of 8.7 mA to 31.7 mA.
The AD9121 comes in a 72-lead LFCSP.
Flexible LVDS interface allows word or byte load
Single-carrier W-CDMA ACLR = 82 dBc at 122.88 MHz IF
Analog output: adjustable 8.7 mA to 31.7 mA,
R
L
= 25 Ω to 50 Ω
Integrated 2×/4×/8× interpolator/complex modulator allows
carrier placement anywhere in the DAC bandwidth
Gain, dc offset, and phase adjustment for sideband
suppression
Multiple chip synchronization interfaces
High performance, low noise PLL clock multiplier
Digital inverse sinc filter
Low power: 1.5 W at 1.2 GSPS, 800 mW at 500 MSPS,
full operating conditions
72-lead, exposed paddle LFCSP
PRODUCT HIGHLIGHTS
1.
Ultralow noise and intermodulation distortion (IMD)
enable high quality synthesis of wideband signals from
baseband to high intermediate frequencies (IF).
Proprietary DAC output switching technique enhances
dynamic performance.
Current outputs are easily configured for various single-
ended or differential circuit topologies.
Flexible LVDS digital interface allows the standard 28-wire
bus to be reduced to one-half of the width.
2.
3.
4.
APPLICATIONS
Wireless infrastructure
W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM, LTE
Digital high or low IF synthesis
Transmit diversity
Wideband communications: LMDS/MMDS, point-to-point
COMPANION PRODUCTS
IQ Modulators:
ADL5370, ADL537x
family
IQ Modulators with PLL and VCO:
ADRF6701, ADRF670x
family
Clock Drivers:
AD9516, AD951x
family
Voltage Regulator Design Tool:
ADIsimPower
GENERAL DESCRIPTION
The AD9121 is a dual, 14-bit, high dynamic range digital-to-
analog converter (DAC) that provides a sample rate of 1230 MSPS,
permitting multicarrier generation up to the Nyquist frequency.
TYPICAL SIGNAL CHAIN
COMPLEX BASEBAND
COMPLEX IF
RF
DC
f
IF
LO – f
IF
2
2/4
I DAC
ANTIALIASING
FILTER
AQM
PA
DIGITAL
BASEBAND
PROCESSOR
2
SIN
COS
2/4
Q DAC
LO
AD9121
NOTES
1. AQM = ANALOG QUADRATURE MODULATOR.
09988-001
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks arethe property of their respectiveowners.
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AD9121
TABLE OF CONTENTS
Features .....................................................................................1
Applications...............................................................................1
General Description ..................................................................1
Product Highlights ....................................................................1
Companion Products.................................................................1
Typical Signal Chain..................................................................1
Revision History ........................................................................3
Functional Block Diagram.........................................................4
Specifications.............................................................................5
DC Specifications...................................................................5
Digital Specifications .............................................................6
Digital Input Data Timing Specifications...............................6
AC Specifications...................................................................7
Absolute Maximum Ratings ......................................................8
Thermal Resistance................................................................8
ESD Caution ..........................................................................8
Pin Configuration and Function Descriptions...........................9
Typical Performance Characteristics .......................................11
Terminology ............................................................................17
Theory of Operation................................................................18
Serial Port Operation ...........................................................18
Data Format.........................................................................18
Serial Port Pin Descriptions.................................................18
Serial Port Options...............................................................19
Device Configuration Register Map and Descriptions.........20
LVDS Input Data Ports ............................................................31
Word Interface Mode...........................................................31
Byte Interface Mode.............................................................31
Interface Timing ..................................................................31
Recommended Frame Input Bias Circuitry .........................32
FIFO Operation ...................................................................32
Digital Datapath ......................................................................36
Premodulation .....................................................................36
Interpolation Filters .............................................................36
NCO Modulation.................................................................39
Datapath Configuration.......................................................39
Determining Interpolation Filter Modes..............................40
Datapath Configuration Examples.......................................41
Data Rates vs. Interpolation Modes .....................................42
Rev. B | Page 2 of 60
Data Sheet
Coarse Modulation Mixing Sequences ................................ 42
Quadrature Phase Correction.............................................. 43
DC Offset Correction .......................................................... 43
Inverse Sinc Filter ................................................................ 43
DAC Input Clock Configurations............................................ 44
Driving the DACCLK and REFCLK Inputs ......................... 44
Direct Clocking ................................................................... 44
Clock Multiplication............................................................ 44
PLL Settings......................................................................... 45
Configuring the VCO Tuning Band..................................... 45
Analog Outputs ....................................................................... 46
Transmit DAC Operation .................................................... 46
Auxiliary DAC Operation.................................................... 47
Interfacing to Modulators.................................................... 48
Baseband Filter Implementation.......................................... 48
Driving the ADL5375-15..................................................... 48
Reducing LO Leakage and Unwanted Sidebands................. 49
Device Power Management ..................................................... 50
Power Dissipation................................................................ 50
Temperature Sensor............................................................. 51
Multichip Synchronization...................................................... 52
Synchronization with Clock Multiplication ............................ 52
Synchronization with Direct Clocking................................. 53
Data Rate Mode Synchronization ........................................ 53
FIFO Rate Mode Synchronization ....................................... 54
Additional Synchronization Features................................... 55
Interrupt Request Operation ................................................... 56
Interrupt Service Routine .................................................... 56
Interface Timing Validation .................................................... 57
SED Operation .................................................................... 57
SED Example ....................................................................... 58
Example Start-Up Routine....................................................... 59
Device Configuration .......................................................... 59
Derived PLL Settings ........................................................... 59
Derived NCO Settings ......................................................... 59
Start-Up Sequence ............................................................... 59
Outline Dimensions ................................................................ 60
Ordering Guide ................................................................... 60
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
AD9121
T
MIN
to T
MAX
, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I
FS
= 20 mA, maximum sample rate, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
MAIN DAC OUTPUTS
Offset Error
Gain Error (with Internal Reference)
Full-Scale Output Current
1
Output Compliance Range
Power Supply Rejection Ratio, AVDD33
Output Resistance
Gain DAC Monotonicity
Settling Time to Within ±0.5 LSB
MAIN DAC TEMPERATURE DRIFT
Offset
Gain
Reference Voltage
REFERENCE
Internal Reference Voltage
Output Resistance
ANALOG SUPPLY VOLTAGES
AVDD33
CVDD18
DIGITAL SUPPLY VOLTAGES
DVDD18
IOVDD
POWER CONSUMPTION
2× Mode, f
DAC
= 491.22 MSPS, IF = 10 MHz, PLL Off
2× Mode, f
DAC
= 491.22 MSPS, IF = 10 MHz, PLL On
8× Mode, f
DAC
= 800 MSPS, IF = 10 MHz, PLL Off
AVDD33
CVDD18
DVDD18
Power-Down Mode (Register 0x01 = 0xF0)
POWER-UP TIME
OPERATING RANGE
1
Min
Typ
14
±0.5
±1.0
Max
Unit
Bits
LSB
LSB
−0.001
−3.6
8.66
−1.0
−0.3
0
±2
19.6
+0.001
+3.6
31.66
+1.0
+0.3
10
Guaranteed
20
0.04
100
30
1.2
5
3.13
1.71
1.71
1.71
3.3
1.8
1.8
1.8/3.3
834
913
1135
55
85
444
6.5
260
+25
3.47
1.89
1.89
3.47
% FSR
% FSR
mA
V
% FSR/V
MΩ
ns
ppm/°C
ppm/°C
ppm/°C
V
kΩ
V
V
V
V
mW
mW
mW
mA
mA
mA
mW
ms
°C
1241
57
90
495
18.8
+85
−40
Based on a 10 kΩ external resistor between FSADJ and AVSS.
Rev. B | Page 5 of 60
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