PIC32MX1XX/2XX
PIC32MX1XX/2XX Family
Silicon Errata and Data Sheet Clarification
The PIC32MX1XX/2XX family devices that you have
received conform functionally to the current Device Data
Sheet (DS61168D), except for the anomalies described
in this document.
The errata described in this document will be addressed
in future revisions of the PIC32MX1XX/2XX silicon.
Note:
The silicon issues discussed in the
following pages are for silicon revisions
with the Device and Revision IDs listed in
Table 1
and
Table 2.
The last column of
each table represents the latest silicon
revision for the devices listed. The silicon
issues are summarized in
Table 3.
For example, to identify the silicon revision level
using MPLAB IDE in conjunction with a hardware
debugger:
1.
2.
3.
4.
Using the appropriate interface, connect
the device to the hardware debugger.
Open an MPLAB project.
Configure the MPLAB project for the appro-
priate device and hardware debugger.
Based on the version of MPLAB you are
using, do one of the following:
a) For MPLAB 8, select
Programmer >
Reconnect.
b) For MPLAB X, select
Window > Dash-
board
and then click the
Refresh
Debug Tool Status
icon (
).
Depending on the development tool used,
the part number and the Device and Revi-
sion ID values appear in the
Output
win-
dow.
If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
Data Sheet clarifications and corrections start on
page 6,
following the discussion of silicon issues.
The silicon revision level can be identified using the
current version of MPLAB
®
IDE and Microchip’s
programmers, debuggers and emulation tools, which
are available at the Microchip corporate web site
(www.microchip.com).
5.
Note:
The Device and Revision ID values for the various
silicon revisions are provided in
Table 1
and
Table 2.
TABLE 1:
SILICON DEVREV VALUES FOR DEVICES WITH 16/32 KB FLASH
Part Number
Device
ID
(1)
Revision ID for Silicon Revision
(1)
A0
A1
PIC32MX110F016B
PIC32MX110F016C
PIC32MX110F016D
PIC32MX210F016B
PIC32MX210F016C
PIC32MX210F016D
PIC32MX120F032B
PIC32MX120F032C
PIC32MX120F032D
PIC32MX220F032B
PIC32MX220F032C
PIC32MX220F032D
Note 1:
0x04A07053
0x04A09053
0x04A0B053
0x04A01053
0x04A03053
0x04A05053
0x04A06053
0x04A08053
0x04A0A053
0x04A00053
0x04A02053
0x04A04053
0x0
0x1
Refer to the
“PIC32MX Flash Programming Specification”
(DS61145) for detailed information on Device
and Revision IDs for your specific device.
©
2011-2012 Microchip Technology Inc.
DS80531C-page 1
PIC32MX1XX/2XX
TABLE 2:
SILICON DEVREV VALUES FOR DEVICES WITH 64/128 KB FLASH
Part Number
PIC32MX130F064B
PIC32MX130F064C
PIC32MX130F064D
PIC32MX230F064B
PIC32MX230F064C
PIC32MX230F064D
PIC32MX150F128B
PIC32MX150F128C
PIC32MX150F128D
PIC32MX250F128B
PIC32MX250F128C
PIC32MX250F128D
Note 1:
Device
ID
(1)
Revision ID for Silicon Revision
(1)
A0
0x04D07053
0x04D09053
0x04D0B053
0x04D01053
0x04D03053
0x04D05053
0x04D08053
0x04D08053
0x04D0A053
0x04D00053
0x04D02053
0x04D04053
0x0
0x1
A1
Refer to the
“PIC32MX Flash Programming Specification”
(DS61145) for detailed information on Device
and Revision IDs for your specific device.
DS80531C-page 2
©
2011-2012 Microchip Technology Inc.
PIC32MX1XX/2XX
TABLE 3:
SILICON ISSUE SUMMARY
Affected Device
Module
Feature
Item #
Issue Summary
Silicon
Flash
Memory Revision
(KB)
A0 A1
16/32
64/128
16/32
64/128
16/32
64/128
16/32
64/128
16/32
64/128
16/32
64/128
16/32
64/128
16/32
64/128
16/32
64/128
16/32
64/128
16/32
64/128
16/32
64/128
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Voltage
Regulator
BOR
1.
Device may not exit Brown-out Reset (BOR) state if a
BOR event occurs.
If a Fail-Safe Clock Monitor (FSCM) event occurs when
Primary Oscillator (P
OSC
) mode is used, firmware clock
switch requests to switch from FRC mode will fail.
The I
2
C module does not respond to address 0x78 when
the STRICT and A10M bits are cleared in the I2CxCON
register.
UIDLE interrupts cease if the UIDLE interrupt flag is
cleared.
The DNL parameter of the ADC module is not within the
published data sheet specifications when the ADC
module is operating at maximum conversion rate.
Open selection for Channel 0 positive input is not
functional.
The ADC module conversion triggers occur on the rising
edge of the INT0 signal even when INT0 is configured to
generate an interrupt on the falling edge.
When the Parallel Master Port (PMP) module is enabled,
address pins cannot be used as GPIO output pins.
Output High Voltage (V
OH
) on pins RA0 and RA1 is not
within the published data sheet specification.
A data write operation by the CPU to a peripheral may be
repeated if an interrupt occurs during initial write
operation.
A clock signal is present on the CLKO pin, regardless of
the clock source and setting of the CLKO Enable
Configuration bit, during a Power-on Reset (POR)
condition.
All input capture modes selectable by ICM<2:0>, with the
exception of Interrupt-only mode, will not work when the
CPU enters Idle mode or Sleep mode.
Oscillator
Clock Switch
2.
I2C™
Slave Mode
3.
USB
UIDLE
Interrupt
4.
ADC
—
5
ADC
CTMU
Calibration
Conversion
Trigger from
INT0 Interrupt
Address Pins
6.
ADC
Parallel
Master Port
(PMP)
I/O Ports
7.
8.
RA0 and RA1
Output
Data Write to
a Peripheral
9.
CPU
10.
Oscillator
Input
Capture
Clock Out
Idle Mode and
Sleep Mode
11.
12
Legend:
An ‘X’ indicates the issue is present in this revision of silicon;
Shaded cells with an Em dash (‘—’) indicate that this silicon revision does not exist for this issue;
Blank cells indicate an issue has been corrected in this revision of silicon.
©
2011-2012 Microchip Technology Inc.
DS80531C-page 3
PIC32MX1XX/2XX
Silicon Errata Issues
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. The table
provided in each issue indicates which
issues exist for a particular revision of
silicon based on memory size.
3. Module: I
2
C™
The slave address, 0x78, is one of a group of
reserved addresses. It is used as the upper byte of
a 10-bit address when 10-bit addressing is
enabled. The I
2
C module control register allows
the programmer to enable both 10-bit addressing
and strict enforcement of reserved addressing,
with the A10M and STRICT bits, respectively.
When both bits are cleared, the device should
respond to the reserved address 0x78, but it does
not.
Work around
None.
1. Module: Voltage Regulator
Device may not exit the Brown-out Reset (BOR)
state if a BOR event occurs.
Work arounds
Work around 1:
V
DD
must remain within the published specification
(see parameter DC10 of the device data sheet).
Work around 2:
Reset the device by providing the Power-on Reset
(POR) condition.
Affected Silicon Revisions
Device Flash
Memory (KB)
16/32
64/128
Device Silicon Revision
A0
X
X
A1
X
X
Affected Silicon Revisions
Device Flash
Memory (KB)
16/32
64/128
Device Silicon Revision
A0
X
X
A1
4. Module: USB
If the bus has been idle for more than 3 ms, the
UIDLE interrupt flag is set. If software clears the
interrupt flag and the bus remains idle, the UIDLE
interrupt flag will not be set again.
Work around
Software can leave the UIDLE bit set until it has
received some indication of bus resumption (i.e.,
Resume, Reset, SOF, or Error).
Note:
Resume and Reset are the only interrupts
that should be following UIDLE assertion.
If the UIDLE bit is set, it should be okay to
suspend the USB module (as long as this
code is protected by the GUARD and/or
ACTPEND logic). This will require soft-
ware to clear the UIDLE interrupt enable
bit to exit the USB ISR (if using interrupt
driven code).
2. Module: Oscillator
If the Primary Oscillator (P
OSC
) mode is
implemented and a Fail-Safe Clock Monitor
(FSCM) event occurs (failure of the external
primary clock), the internal clock source will switch
to the FRC oscillator. Subsequent firmware clock
switch requests from the FRC oscillator to other
clock sources will fail and the device will continue
to execute on the FRC oscillator. On repair of the
external clock source and a power-on state, the
device will resume operation with the primary
oscillator clock source.
Work around
None.
Affected Silicon Revisions
Device Flash
Memory (KB)
16/32
64/128
Device Silicon Revision
A0
X
X
A1
X
X
Affected Silicon Revisions
Device Flash
Memory (KB)
16/32
64/128
Device Silicon Revision
A0
X
X
A1
X
X
DS80531C-page 4
©
2011-2012 Microchip Technology Inc.
PIC32MX1XX/2XX
5. Module: ADC
If the ADC module is configured to operate at a
maximum conversion rate of 1.1 Msps, missing
codes are possible every 2
5
codes and the DNL
parameter will not be within the published
specification.
Work around
Configure the ADC module to operate for a
maximum conversion rate of 500 ksps.
7. Module: ADC
When the ADC module is configured to start
conversion
on
an
external
interrupt
(SSRC<2:0> =
001),
the start of conversion
always occurs on a rising edge detected at the
INT0 pin, even when the INT0 pin has been
configured to generate an interrupt on a falling
edge (INT0EP =
0).
Work around
Generate ADC conversion triggers on the rising
edge of the INT0 signal.
Alternately, use external circuitry to invert the
signal appearing at the INT0 pin, so that a falling
edge of the input signal is detected as a rising
edge by the INT0 pin.
Affected Silicon Revisions
Device Flash
Memory (KB)
16/32
64/128
Device Silicon Revision
A0
X
X
A1
X
X
6. Module: ADC
If the ADC module is used in conjunction with the
CTMU module in Absolute Capacitive/Time
Measurement mode, Channel 0 positive input
must remain open (CH0SA<3:0> =
1111
or
CH0SB<3:0> =
1111)
during calibration step.
However, open selection for Channel 0 positive
input is not functional and connects this input to
AV
SS
.
Work around
Use the ADC and CTMU modules for relative
capacitive/time measurement, where calibration
step is not required.
Affected Silicon Revisions
Device Flash
Memory (KB)
16/32
64/128
Device Silicon Revision
A0
X
X
A1
X
X
8. Module: Parallel Master Port (PMP)
If the PMP module is enabled, any pin with a PMP
addressing capability (PMAx) cannot be used as a
general purpose output pin, even when the
corresponding PTEN<10:0> bit in the PMAEN
register is cleared. All other functionality on these
pins, including GPIO input functionality is not
affected.
Work around
To use a GPIO pin as an output when this pin is
shared with PMP addressing functionality and
PMP is enabled, do the following:
1.
Enable PMP addressing by setting the
corresponding PTEN<10:0> bit in the
PMAEN register.
Instead of using corresponding LATx
registers to output GPIO data, use the
PMADDR register.
Affected Silicon Revisions
Device Flash
Memory (KB)
16/32
64/128
Device Silicon Revision
A0
X
A1
X
2.
Affected Silicon Revisions
Device Flash
Memory (KB)
16/32
64/128
Device Silicon Revision
A0
X
X
A1
X
X
©
2011-2012 Microchip Technology Inc.
DS80531C-page 5
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