LCMXO2-256HC-4TG100C datasheet, PDF

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LCMXO2-256HC-4TG100C: DescriptionCPLD MachXO2 Family 2.5V/3.3V 100-Pin TQFP Tray; CategoryProgrammable logic devices Programmable logic; File Size3MB，122 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com; Environmental Compliance

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LCMXO2-256HC-4TG100C Overview

CPLD MachXO2 Family 2.5V/3.3V 100-Pin TQFP Tray

LCMXO2-256HC-4TG100C Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Lattice
Parts packaging code	QFP
package instruction	LFQFP, QFP100,.63SQ,20
Contacts	100
Reach Compliance Code	compliant
ECCN code	EAR99
Samacsys Description	MachXO2, TQFP-100
JESD-30 code	S-PQFP-G100
JESD-609 code	e3
length	14 mm
Humidity sensitivity level	3
Dedicated input times
Number of I/O lines
Number of entries	56
Number of logical units	256
Output times	56
Number of terminals	100
Maximum operating temperature	85 °C
Minimum operating temperature
organize	0 DEDICATED INPUTS, 0 I/O
Output function	MIXED
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP100,.63SQ,20
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
power supply	2.5/3.3 V
Programmable logic type	FLASH PLD
propagation delay	7.36 ns
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage	3.462 V
Minimum supply voltage	2.375 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	14 mm
Base Number Matches	1

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MachXO2 Family Data Sheet

Data Sheet

FPGA-DS-02056-3.7

June 2021

MachXO2 Family Data Sheet

Data Sheet

Contents

Acronyms in This Document ................................................................................................................................................. 9

1. Introduction ................................................................................................................................................................ 10

1.1. Features ............................................................................................................................................................ 11

1.1.1. Flexible Logic Architecture ....................................................................................................................... 11

1.1.2. Ultra Low Power Devices .......................................................................................................................... 11

1.1.3. Embedded and Distributed Memory ........................................................................................................ 11

1.1.4. On-Chip User Flash Memory .................................................................................................................... 11

1.1.5. Pre-Engineered Source Synchronous I/O ................................................................................................. 11

1.1.6. High Performance, Flexible I/O Buffer ..................................................................................................... 11

1.1.7. Flexible On-Chip Clocking ......................................................................................................................... 11

1.1.8. Non-volatile, Infinitely Reconfigurable..................................................................................................... 11

1.1.9. TransFR™ Reconfiguration ....................................................................................................................... 11

1.1.10. Enhanced System Level Support .............................................................................................................. 11

1.1.11. Broad Range of Package Options ............................................................................................................. 11

2. Architecture ................................................................................................................................................................ 14

2.1. Architecture Overview ...................................................................................................................................... 14

2.2. PFU Blocks......................................................................................................................................................... 15

2.2.1. Slices ......................................................................................................................................................... 16

2.2.2. Modes of Operation ................................................................................................................................. 17

2.2.3. RAM Mode ............................................................................................................................................... 18

2.2.4. ROM Mode ............................................................................................................................................... 18

2.3. Routing.............................................................................................................................................................. 18

2.4. Clock/Control Distribution Network ................................................................................................................. 18

2.4.1. sysCLOCK Phase Locked Loops (PLLs) ....................................................................................................... 20

2.5. sysMEM Embedded Block RAM Memory ......................................................................................................... 23

2.6. Programmable I/O Cells (PIC) ........................................................................................................................... 27

2.7. PIO .................................................................................................................................................................... 29

2.7.1. Input Register Block.................................................................................................................................. 29

2.7.2. Output Register Block............................................................................................................................... 31

2.7.3. Tri-state Register Block............................................................................................................................. 32

2.8. Input Gearbox ................................................................................................................................................... 32

2.9. Output Gearbox ................................................................................................................................................ 34

2.10. DDR Memory Support....................................................................................................................................... 36

2.11. DQS Read Write Block....................................................................................................................................... 36

2.12. sysI/O Buffer ..................................................................................................................................................... 36

2.12.1. Typical I/O Behavior During Power-up ..................................................................................................... 37

2.12.2. Supported Standards ................................................................................................................................ 37

2.12.3. sysI/O Buffer Banks .................................................................................................................................. 40

2.13. Hot Socketing .................................................................................................................................................... 41

2.14. On-chip Oscillator ............................................................................................................................................. 41

2.15. Embedded Hardened IP Functions and User Flash Memory ............................................................................ 42

2.15.1. Hardened I

C IP Core ................................................................................................................................ 43

2.15.2. Hardened SPI IP Core................................................................................................................................ 44

2.15.3. Hardened Timer/Counter ......................................................................................................................... 45

2.16. User Flash Memory (UFM) ................................................................................................................................ 46

2.17. Standby Mode and Power Saving Options ....................................................................................................... 47

2.18. Power-On-Reset................................................................................................................................................ 48

2.19. Configuration and Testing ................................................................................................................................ 49

2.19.1. IEEE 1149.1-Compliant Boundary Scan Testability ................................................................................... 49

2.19.2. Device Configuration ................................................................................................................................ 49

2.20. TraceID .............................................................................................................................................................. 50

2.21. Density Shifting ................................................................................................................................................. 50

www.latticesemi.com/legal.

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02056-3.7

MachXO2 Family Data Sheet

Data Sheet

DC and Switching Characteristics................................................................................................................................51

3.1. Absolute Maximum Ratings ..............................................................................................................................51

3.2. Recommended Operating Conditions...............................................................................................................51

3.3. Power Supply Ramp Rates ................................................................................................................................51

3.4. Power-On-Reset Voltage Levels ........................................................................................................................52

3.5. Programming/Erase Specifications ...................................................................................................................52

3.6. Hot Socketing Specifications .............................................................................................................................52

3.7. ESD Performance ..............................................................................................................................................52

3.8. DC Electrical Characteristics..............................................................................................................................53

3.9. Static Supply Current – ZE Devices....................................................................................................................54

3.10. Static Power Consumption Contribution of Different Components – ZE Devices ............................................54

3.11. Static Supply Current – HC/HE Devices .............................................................................................................55

3.12. Programming and Erase Flash Supply Current – HC/HE Devices ......................................................................56

3.13. Programming and Erase Flash Supply Current – ZE Devices .............................................................................56

3.14. sysI/O Recommended Operating Conditions....................................................................................................57

3.15. sysI/O Single-Ended DC Electrical Characteristics .............................................................................................58

3.16. sysI/O Differential Electrical Characteristics .....................................................................................................59

3.16.1. LVDS ..........................................................................................................................................................59

3.16.2. LVDS Emulation ........................................................................................................................................60

3.16.3. BLVDS........................................................................................................................................................61

3.16.4. LVPECL ......................................................................................................................................................62

3.16.5. RSDS ..........................................................................................................................................................63

3.17. Typical Building Block Function Performance – HC/HE Devices .......................................................................64

3.17.1. Pin-to-Pin Performance (LVCMOS25 12 mA Drive) ..................................................................................64

3.17.2. Register-to-Register Performance ............................................................................................................64

3.18. Typical Building Block Function Performance – ZE Devices ..............................................................................65

3.18.1. Pin-to-Pin Performance (LVCMOS25 12 mA Drive) ..................................................................................65

3.18.2. Register-to-Register Performance ............................................................................................................65

3.19. Derating Logic Timing .......................................................................................................................................65

3.20. Maximum sysI/O Buffer Performance ..............................................................................................................66

3.21. MachXO2 External Switching Characteristics – HC/HE Devices ........................................................................67

3.22. MachXO2 External Switching Characteristics – ZE Devices...............................................................................73

3.23. sysCLOCK PLL Timing .........................................................................................................................................81

3.24. MachXO2 Oscillator Output Frequency ............................................................................................................82

3.25. MachXO2 Standby Mode Timing – HC/HE Devices ...........................................................................................82

3.26. MachXO2 Standby Mode Timing – ZE Devices .................................................................................................83

3.27. Flash Download Time ........................................................................................................................................83

3.28. JTAG Port Timing Specifications ........................................................................................................................84

3.29. sysCONFIG Port Timing Specifications ..............................................................................................................85

3.30. I

C Port Timing Specifications ...........................................................................................................................86

3.31. SPI Port Timing Specifications ...........................................................................................................................86

3.32. Switching Test Conditions .................................................................................................................................86

Pinout Information .....................................................................................................................................................88

4.1. Signal Descriptions ............................................................................................................................................88

4.2. Pinout Information Summary ...........................................................................................................................90

4.3. For Further Information ....................................................................................................................................95

4.4. Thermal Management ......................................................................................................................................95

4.4.1. For Further Information ...........................................................................................................................95

Ordering Information..................................................................................................................................................96

5.1. MachXO2 Part Number Description .................................................................................................................96

5.2. Ordering Information ........................................................................................................................................97

5.2.1. Ultra Low Power Commercial Grade Devices, Halogen Free (RoHS) Packaging .......................................97

5.2.2. High-Performance Commercial Grade Devices with Voltage Regulator,

Halogen Free (RoHS) Packaging .............................................................................................................99

www.latticesemi.com/legal.

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02056-3.7

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