SO
T3
23
PDTD1xxxU series
500 mA, 50 V NPN resistor-equipped transistors
Rev. 1 — 13 May 2014
Product data sheet
1. Product profile
1.1 General description
NPN Resistor-Equipped Transistor (RET) family in a very small SOT323 (SC-70)
Surface-Mounted Device (SMD) plastic package.
Table 1.
Product overview
Package
NXP
PDTD113EU
PDTD113ZU
PDTD123EU
PDTD123YU
PDTD143EU
PDTD143XU
PDTD114EU
SOT323
JEITA
SC-70
JEDEC
-
PNP
complement
PDTB113EU
PDTB113ZU
PDTB123EU
PDTB123YU
PDTB143EU
PDTB143XU
PDTB114EU
Package
configuration
very small
Type number
1.2 Features
500 mA output current capability
Built-in bias resistors
Simplifies circuit design
Reduces component count
10 % resistor ratio tolerance
AEC-Q101 qualified
High temperature applications
up to 175 °C
1.3 Applications
IC inputs control
Cost-saving alternative to BC807 or
BC817 series transistors in digital
applications
Switching loads
NXP Semiconductors
PDTD1xxxU series
500 mA, 50 V NPN resistor-equipped transistors
1.4 Quick reference data
Table 2.
Symbol
V
CEO
I
O
R1
Quick reference data
Parameter
collector-emitter voltage
output current
bias resistor 1 (input)
PDTD113EU
PDTD113ZU
PDTD123EU
PDTD123YU
PDTD143EU
PDTD143XU
PDTD114EU
R2
bias resistor 2 (base-emitter)
PDTD113EU
PDTD113ZU
PDTD123EU
PDTD123YU
PDTD143EU
PDTD143XU
PDTD114EU
1
10
2.2
10
4.7
10
10
k
k
k
k
k
k
k
1
1
2.2
2.2
4.7
4.7
10
k
k
k
k
k
k
k
Conditions
open base
Min
-
-
Typ
-
-
Max
50
500
Unit
V
mA
2. Pinning information
Table 3.
Pin
1
2
3
Pinning
Description
input (base)
GND (emitter)
output (collector)
1
2
2
sym007
Simplified outline
3
Graphic symbol
3
R1
1
R2
3. Ordering information
Table 4.
Ordering information
Package
Name
PDTD1xxxU series
SC-70
Description
plastic surface-mounted package; 3 leads
Version
SOT323
Type number
PDTD1XXXU_SER
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 13 May 2014
2 of 27
NXP Semiconductors
PDTD1xxxU series
500 mA, 50 V NPN resistor-equipped transistors
4. Marking
Table 5.
Marking codes
Marking code
[1]
ZP*
ZQ*
ZR*
ZS*
ZT*
ZU*
ZV*
Type number
PDTD113EU
PDTD113ZU
PDTD123EU
PDTD123YU
PDTD143EU
PDTD143XU
PDTD114EU
[1]
* = placeholder for manufacturing site code
5. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
CBO
V
CEO
V
EBO
Parameter
collector-base voltage
collector-emitter voltage
emitter-base voltage
PDTD113EU
PDTD113ZU
PDTD123EU
PDTD123YU
PDTD143EU
PDTD143XU
PDTD114EU
V
I
input voltage
PDTD113EU
PDTD113ZU
PDTD123EU
PDTD123YU
PDTD143EU
PDTD143XU
PDTD114EU
I
O
output current
10
5
10
5
10
7
10
-
+10
+10
+12
+12
+30
+30
+50
500
V
V
V
V
V
V
V
mA
Conditions
open emitter
open base
open collector
-
-
-
-
-
-
-
10
5
10
5
10
7
10
V
V
V
V
V
V
V
Min
-
-
Max
50
50
Unit
V
V
PDTD1XXXU_SER
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 13 May 2014
3 of 27
NXP Semiconductors
PDTD1xxxU series
500 mA, 50 V NPN resistor-equipped transistors
Table 6.
Limiting values
…continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
P
tot
T
j
T
amb
T
stg
[1]
[2]
Parameter
total power dissipation
junction temperature
ambient temperature
storage temperature
Conditions
T
amb
25
C
[1]
[2]
Min
-
-
-
55
55
Max
300
425
175
+175
+175
Unit
mW
mW
C
C
C
Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard
footprint.
Device mounted on an FR4 PCB, 4-layer copper, tin-plated and standard footprint.
500
P
tot
(mW)
400
(1)
aaa-012426
(2)
300
200
100
0
-75
25
125
T
amb
(°C)
225
(1) FR4 PCB, 4-layer copper, standard footprint
(2) FR4 PCB, single-sided copper, standard footprint.
Fig 1.
Power derating curves
6. Thermal characteristics
Table 7.
Symbol
R
th(j-a)
Thermal characteristics
Parameter
thermal resistance from junction
to ambient
Conditions
in free air
[1]
[2]
Min
-
-
Typ
-
-
Max
500
353
Unit
K/W
K/W
[1]
[2]
Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
Device mounted on an FR4 PCB, 4-layer copper, tin-plated and standard footprint.
PDTD1XXXU_SER
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 13 May 2014
4 of 27
NXP Semiconductors
PDTD1xxxU series
500 mA, 50 V NPN resistor-equipped transistors
10
3
duty cycle = 1
Z
th(j-a)
(K/W)
10
2
0.75
0.33
0.2
0.1
0.05
10
0.02
0.01
0.5
aaa-012062
1
0
10
-1
10
-5
10
-4
10
-3
10
-2
10
-1
1
10
10
2
t
p
(s)
10
3
FR4 PCB, single-sided copper, tin-plated and standard footprint
Fig 2.
Transient thermal impedance from junction to ambient as a function of pulse duration for SOT323/SC-70;
typical values
aaa-012063
10
3
Z
th(j-a)
(K/W)
10
2
duty cycle = 1
0.75
0.5
0.33
0.2
0.1
0.05
10
0.02
0.01
0
1
10
-5
10
-4
10
-3
10
-2
10
-1
1
10
10
2
t
p
(s)
10
3
FR4 PCB, 4-layer copper, tin-plated and standard footprint.
Fig 3.
Transient thermal impedance from junction to ambient as a function of pulse duration for SOT323/SC-70;
typical values
PDTD1XXXU_SER
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 13 May 2014
5 of 27
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