ispGDX
®
160V/VA Device Datasheet
June 2010
Select Devices Discontinued!
Product Change Notification (PCN) #09-10 has been issued to discontinue select devices
in this data sheet.
The original datasheet pages have not been modified and do not reflect those changes.
Please refer to the table below for reference PCN and current product status.
Product Line
Ordering Part Number
ispGDX160V-5B272
ispGDX160V-7B272
ispGDX160V-5B208
ispGDX160V-7B208
ispGDX160V-5Q208
ispGDX160V-7Q208
ispGDX160V-7Q208I
ispGDX160VA-3B272
ispGDX160VA-5B272
ispGDX160VA-7B272
ispGDX160VA-5B272I
ispGDX160VA-7B272I
ispGDX160VA-9B272I
ispGDX160VA-3Q208
ispGDX160VA-5Q208
ispGDX160VA-7Q208
ispGDX160VA-5Q208I
ispGDX160VA-7Q208I
ispGDX160VA-9Q208I
ispGDX160VA-3B208
ispGDX160VA-3BN208
ispGDX160VA-5B208
ispGDX160VA-5BN208
ispGDX160VA-7B208
ispGDX160VA-7BN208
ispGDX160VA-5B208I
ispGDX160VA-5BN208I
ispGDX160VA-7B208I
ispGDX160VA-7BN208I
ispGDX160VA-9B208I
ispGDX160VA-9BN208I
Product Status
Discontinued
Reference PCN
PCN#09-10
ispGDX160V
Active / Orderable
Discontinued
PCN#09-10
ispGDX160VA
Active / Orderable
5555 N.E. Moore Ct.
Hillsboro, Oregon 97124-6421 Phone (503) 268-8000
Internet: http://www.latticesemi.com
FAX (503) 268-8347
Lead-
Free
Package
Options
Available!
ispGDX 160V/VA
In-System Programmable
3.3V Generic Digital Crosspoint
Functional Block Diagram
I/O Pins D
ISP
Control
®
Features
• IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL
CROSSPOINT FAMILY
— Advanced Architecture Addresses Programmable
PCB Interconnect, Bus Interface Integration and
Jumper/Switch Replacement
— “Any Input to Any Output” Routing
— Fixed HIGH or LOW Output Option for Jumper/DIP
Switch Emulation
— Space-Saving PQFP and BGA Packaging
— Dedicated IEEE 1149.1-Compliant Boundary Scan
Test
SE
LE
D
IS C
C T
O D
N E
TI VI
N C
U E
ED S
I/O Pins C
I/O Pins A
I/O
Cells
Global Routing
Pool
(GRP)
I/O
Cells
• HIGH PERFORMANCE E
2
CMOS
®
TECHNOLOGY
— 3.3V Core Power Supply
— 3.5ns Input-to-Output/3.5ns Clock-to-Output Delay*
— 250MHz Maximum Clock Frequency*
— TTL/3.3V/2.5V Compatible Input Thresholds and
Output Levels (Individually Programmable)*
— Low-Power: 16.5mA Quiescent Icc*
— 24mA I
OL
Drive with Programmable Slew Rate
Control Option
— PCI Compatible Drive Capability*
— Schmitt Trigger Inputs for Noise Immunity
— Electrically Erasable and Reprogrammable
— Non-Volatile E
2
CMOS Technology
Boundary
Scan
Control
I/O Pins B
Description
• ispGDXV OFFERS THE FOLLOWING ADVANTAGES
— 3.3V In-System Programmable Using Boundary Scan
Test Access Port (TAP)
— Change Interconnects in Seconds
The ispGDXV/VA architecture provides a family of fast,
flexible programmable devices to address a variety of
system-level digital signal routing and interface require-
ments including:
• Multi-Port Multiprocessor Interfaces
• FLEXIBLE ARCHITECTURE
— Combinatorial/Latched/Registered Inputs or Outputs
— Individual I/O Tri-state Control with Polarity Control
— Dedicated Clock/Clock Enable Input Pins (four) or
Programmable Clocks/Clock Enables from I/O Pins
(40)
— Single Level 4:1 Dynamic Path Selection (Tpd = 3.5ns)
— Programmable Wide-MUX Cascade Feature
Supports up to 16:1 MUX
— Programmable Pull-ups, Bus Hold Latch and Open
Drain on I/O Pins
— Outputs Tri-state During Power-up (“Live Insertion”
Friendly)
• LEAD-FREE PACKAGE OPTIONS
* “VA” Version Only
• Wide Data and Address Bus Multiplexing
(e.g. 16:1 High-Speed Bus MUX)
• Programmable Control Signal Routing
(e.g. Interrupts, DMAREQs, etc.)
• Board-Level PCB Signal Routing for Prototyping or
Programmable Bus Interfaces
The devices feature fast operation, with input-to-output
signal delays (Tpd) of 3.5ns and clock-to-output delays of
3.5ns.
The architecture of the devices consists of a series of
programmable I/O cells interconnected by a Global Rout-
ing Pool (GRP). All I/O pin inputs enter the GRP directly
or are registered or latched so they can be routed to the
required I/O outputs. I/O pin inputs are defined as four
sets (A,B,C,D) which have access to the four MUX inputs
Copyright © 2004 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein
are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
August 2004
gdx160va_06
1
Specifications
ispGDX160V/VA
Description (Continued)
found in each I/O cell. Each output has individual, pro-
grammable I/O tri-state control (OE), output latch clock
(CLK), clock enable (CLKEN), and two multiplexer con-
trol (MUX0 and MUX1) inputs. Polarity for these signals
is programmable for each I/O cell. The MUX0 and MUX1
inputs control a fast 4:1 MUX, allowing dynamic selection
of up to four signal sources for a given output. A wider
16:1 MUX can be implemented with the MUX expander
feature of each I/O and a propagation delay increase of
2.0ns. OE, CLK, CLKEN, and MUX0 and MUX1 inputs
can be driven directly from selected sets of I/O pins.
Optional dedicated clock input pins give minimum clock-
to-output delays. CLK and CLKEN share the same set of
I/O pins. CLKEN disables the register clock when
CLKEN = 0.
In addition, there are no pin-to-pin routing constraints for
1:1 or 1:n signal routing. That is,
any
I/O pin configured
as an input can drive one or more I/O pins configured as
outputs.
The device pins also have the ability to set outputs to
fixed HIGH or LOW logic levels (Jumper or DIP Switch
mode). Device outputs are specified for 24mA sink and
12mA source current (at JEDEC LVTTL levels) and can
be tied together in parallel for greater drive. On the
ispGDXVA, each I/O pin is individually programmable for
3.3V or 2.5V output levels as described later. Program-
mable output slew rate control can be defined
independently for each I/O pin to reduce overall ground
bounce and switching noise.
All I/O pins are equipped with IEEE1149.1-compliant
Boundary Scan Test circuitry for enhanced testability. In
addition, in-system programming is supported through
the Test Access Port via a special set of private com-
mands.
The ispGDXV I/Os are designed to withstand “live inser-
tion” system environments. The I/O buffers are disabled
during power-up and power-down cycles. When design-
ing for “live insertion,” absolute maximum rating conditions
for the Vcc and I/O pins must still be met.
SE
LE
D
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Through in-system programming, connections between
I/O pins and architectural features (latched or registered
inputs or outputs, output enable control, etc.) can be
defined. In keeping with its data path application focus,
the ispGDXV devices contain no programmable logic
arrays. All input pins include Schmitt trigger buffers for
noise immunity. These connections are programmed
into the device using non-volatile E
2
CMOS technology.
Non-volatile technology means the device configuration
is saved even when the power is removed from the
device.
Table 1. ispGDXV Family Members
ispGDXVA Device
ispGDX160VA
160
40
40
ispGDX80VA
80
20
20
20
20
2
1
1
4
1
ispGDX240VA
240
60
60
60
60
4
1
1
4
1
I/O Pins
I/O-OE Inputs*
I/O-CLK / CLKEN Inputs*
I/O-MUXsel1 Inputs*
I/O-MUXsel2 Inputs*
EPEN
40
40
4
1
Dedicated Clock Pins**
TOE
BSCAN Interface
RESET
1
4
1
Pin Count/Package
100-Pin TQFP
208-Pin PQFP 388-Ball fpBGA
208-Ball fpBGA
272-Ball BGA
* The CLK/CLK_EN, OE, MUX0 and MUX1 terminals on each I/O cell can each be assigned to
25% of the I/Os.
** Global clock pins Y0, Y1, Y2 and Y3 are multiplexed with CLKEN0, CLKEN1, CLKEN2 and
CLKEN3 respectively in all devices.
2
Specifications
ispGDX160V/VA
Architecture
The ispGDXV/VA architecture is different from traditional
PLD architectures, in keeping with its unique application
focus. The block diagram is shown below. The program-
mable interconnect consists of a single Global Routing
Pool (GRP). Unlike ispLSI
®
devices, there are no pro-
grammable logic arrays on the device. Control signals for
OEs, Clocks/Clock Enables and MUX Controls must
come from designated sets of I/O pins. The polarity of
these signals can be independently programmed in each
I/O cell.
The various I/O pin sets are also shown in the block
diagram below. The A, B, C, and D I/O pins are grouped
together with one group per side.
SE
LE
D
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Each I/O cell drives a unique pin. The OE control for each
I/O pin is independent and may be driven via the GRP by
one of the designated I/O pins (I/O-OE set). The I/O-OE
set consists of 25% of the total I/O pins. Boundary Scan
test is supported by dedicated registers at each I/O pin.
In-system programming is accomplished through the
standard Boundary Scan protocol.
Figure 1. ispGDXV/VA I/O Cell and GRP Detail (160 I/O Device)
Logic “0” Logic “1”
I/O Architecture
Each I/O cell contains a 4:1 dynamic MUX controlled by
two select lines as well as a 4x4 crossbar switch con-
trolled by software for increased routing flexiability (Figure
1). The four data inputs to the MUX (called M0, M1, M2,
and M3) come from I/O signals in the GRP and/or
adjacent I/O cells. Each MUX data input can access one
quarter of the total I/Os. For example, in a 160 I/O
ispGDXV, each data input can connect to one of 40 I/O
pins. MUX0 and MUX1 can be driven by designated I/O
pins called MUXsel1 and MUXsel2. Each MUXsel input
covers 25% of the total I/O pins (e.g. 40 out of 160). MUX0
and MUX1 can be driven from either MUXsel1 or MUXsel2.
160 I/O Inputs
I/OCell 0
I/O Cell 159
I/O Cell 1
I/O Cell 158
E
2
CMOS
•
•
•
Programmable
Interconnect
From MUX Outputs
of 2 Adjacent I/O Cells
To 2 Adjacent
I/O Cells above
Bypass Option
Register
or Latch
N+2
4-to-1 MUX
Prog.
Prog.
Pull-up
Bus Hold
Latch
(VCCIO)
I/O Group A
I/O Group B
I/O Group C
I/O Group D
N+1
N-1
4x4
Crossbar
Switch
•
•
•
•
•
•
N-2
M0
M1
M2
M3
MUX0 MUX1
A
B
C
R
I/O
Pin
D
Q
CLK
Prog. Open Drain
From MUX Outputs
of 2 Adjacent I/O Cells
To 2 Adjacent
I/O Cells below
CLK_EN Reset
2.5V/3.3V Output
Prog. Slew Rate
Boundary
Scan Cell
I/O Cell N
•
•
•
I/O Cell 78
••••••
I/O Cell 81
I/O Cell 79
80 I/O Cells
160 Input GRP
Inputs Vertical
Outputs Horizontal
Y0-Y3
Global
Clocks /
Clock_Enables
Global
Reset
I/O Cell 80
80 I/O Cells
ispGDXV/VA architecture enhancements over ispGDX (5V)
3
Specifications
ispGDX160V/VA
I/O MUX Operation
MUX1
0
0
1
1
MUX0
0
1
1
0
Data Input Selected
M0
M1
M2
M3
SE
LE
D
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Flexible mapping of MUXsel
x
to MUX
x
allows the user to
change the MUX select assignment after the ispGDXV/
VA device has been soldered to the board. Figure 1
shows that the I/O cell can accept (by programming the
appropriate fuses) inputs from the MUX outputs of four
adjacent I/O cells, two above and two below. This en-
ables cascading of the MUXes to enable wider (up to
16:1) MUX implementations.
Device
Normal I/O Cells
TBA
ispGDX80VA
TBA
ispGDX160V/VA B19-B0, A39-A20,
A19-A0, D39-D20
ispGDX240VA
TBA
TBA
I/O cell index increases in this direction
allow adjacent I/O cell outputs to be directly connected
without passing through the global routing pool. The
relationship between the [N+i] adjacent cells and A, B, C
and D inputs will vary depending on where the I/O cell is
located on the physical die. The I/O cells can be grouped
into “normal” and “reflected” I/O cells or I/O “hemi-
spheres.” These are defined as:
Reflected I/O Cells
B20-B39, C0-C19,
C20-C39, D0-D19
MUX Expander Using Adjacent I/O Cells
The ispGDXV/VA allows adjacent I/O cell MUXes to be
cascaded to form wider input MUXes (up to 16 x 1)
without incurring an additional full Tpd penalty. However,
there are certain dependencies on the locality of the
adjacent MUXes when used along with direct MUX
inputs.
B0
B19
B20
B39
I/O cell 79
I/O cell 80
Adjacent I/O Cells
Expansion inputs MUXOUT[n-2], MUXOUT[n-1],
MUXOUT[n+1], and MUXOUT[n+2] are fuse-selectable
for each I/O cell MUX. These expansion inputs share the
same path as the standard A, B, C and D MUX inputs, and
Direct and Expander Input Routing
Table 2 also illustrates the routing of MUX direct inputs
that are accessible when using adjacent I/O cells as
inputs. Take I/O cell D23 as an example, which is also
shown in Figure 3.
4
I/O cell index increases in this direction
The I/O cell also includes a programmable flow-through
latch or register that can be placed in the input or output
path and bypassed for combinatorial outputs. As shown
in Figure 1, when the input control MUX of the register/
latch selects the “A” path, the register/latch gets its inputs
from the 4:1 MUX and drives the I/O output. When
selecting the “B” path, the register/latch is directly driven
by the I/O input while its output feeds the GRP. The
programmable polarity Clock to the latch or register can
be connected to any I/O in the I/O-CLK/CLKEN set (one-
quarter of total I/Os) or to one of the dedicated clock input
pins (Y
x
). The programmable polarity Clock Enable input
to the register can be programmed to connect to any of
the I/O-CLK/CLKEN input pin set or to the global clock
enable inputs (CLKEN
x
). Use of the dedicated clock
inputs gives minimum clock-to-output delays and mini-
mizes delay variation with fanout. Combinatorial output
mode may be implemented by a dedicated architecture
bit and bypass MUX. I/O cell output polarity can be
programmed as active high or active low.
Table 2 shows the relationship between adjacent I/O
cells as well as their relationship to direct MUX inputs.
Note that the MUX expansion is circular and that I/O cell
B20, for example, draws on I/Os B19 and B18, as well as
B21 and B22, even though they are in different hemi-
spheres of the physical die. Table 2 shows some typical
cases and all boundary cases. All other cells can be
extrapolated from the pattern shown in the table.
Figure 2. I/O Hemisphere Configuration of
ispGDX160V/VA
I/O cell 0
I/O cell 159
D39
D20
D19
D0
A0
C39
A39
C0
京公网安备 11010802033920号
EEWORLD
