Operating Temperature Range ......................... -40°C to +125°C
Junction Temperature .......................................Internally Limited
Storage Temperature Range ............................ -65°C to +150°C
Lead Temperature (soldering, 10s)
................................. +300°C
Soldering Temperature (reflow)
.......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics
(Note 1)
Junction-to-Ambient Thermal Resistance (θ
JA
)
..............18°C/W
Junction-to-Case Thermal Resistance (θ
JC
)
.....................1°C/W
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(V
DD
= 10V to 36V, V
5
= 4.5V to 5.5V, V
L
= 2.5V to 5.5V, T
A
= -40°C to +125°C, unless otherwise noted. Typical values are at V
DD
= 24V,
V
5
= 5V, V
L
= 3.3V, and T
A
= +25°C.) (Note 2)
PARAMETER
DC CHARACTERISTICS
V
DD
Supply Voltage
V
DD
Supply Current
V
DD
Disable Supply Current
V
DD
Undervoltage-Lockout
Threshold
V
DD
Undervoltage-Lockout
Hysteresis
V
5
Supply Voltage
V
5
Supply Current
V
5
Undervoltage-Lockout
Threshold
V
5
Undervoltage-Lockout
Hysteresis
V
5
POR Threshold
V
L
Supply Voltage
V
L
Supply Current
V
L
POR Threshold
V
DD
I
DD
I
DD_DIS
VDD_
UVLO
SYMBOL
CONDITIONS
MIN
10
TYP
MAX
36
UNITS
V
mA
EN = high, O_ in push-pull mode
and unloaded
EN = high, O_ in high-side mode
and unloaded
EN = low
V
5
= 5V, V
DD
rising
V
5
= 5V
4.5
O_ in push-pull or high-side mode,
CS
= high, DC output
V
DD
= 24V, V
5
rising
V
DD
= 24V
3.8
7.0
0.7
0.7
0.7
7.8
2.5
1.5
1.5
1.5
8.5
mA
V
V
5.5
V
mA
V
V
2.4
5.5
40
2.4
V
V
µA
V
V
DD_
UVHYS
V
5
I
5
V
5_UVLO
V
5_UVHYS
V
5_POR
V
L
I
L
V
L_POR
Logic inputs unconnected
0.9
4
0.3
1.6
2.5
9
1.6
1.5
4.2
www.maximintegrated.com
Maxim Integrated
│
2
MAX14900E
Octal, High-Speed, Industrial, High-Side Switch
Electrical Characteristics (continued)
(V
DD
= 10V to 36V, V
5
= 4.5V to 5.5V, V
L
= 2.5V to 5.5V, T
A
= -40°C to +125°C, unless otherwise noted. Typical values are at V
DD
= 24V,
V
5
= 5V, V
L
= 3.3V, and T
A
= +25°C.) (Note 2)
PARAMETER
DRIVER OUTPUTS (O_)
High-Side Mode On-Resistance
High-Side Mode Current Limit
High-Side Mode Leakage
Current
Push-Pull Mode On-Resistance
R
ON_HS
I
LIM_HS
I
LKG_HS
R
ON_PP
High-side mode, EN = high, O_ = high,
I
O_
= 500mA
High-side mode, EN = high, O_ = high
EN = low, V
O_
= 0V
Push-pull
mode,
EN = high
Push-pull
mode,
EN = high,
during blanking
time
I
O_
= +50mA,
O_ = high
I
O_
= -50mA, O_ = low
0V < V
O_
< V
DD
- 3V,
O_ = high
3V < V
O_
< V
DD
,
O_ = low
200
200
1.4
-1
1.6
5.2
500
mA
300
90
11
µs
ms
85
1.7
165
2.0
+20
4
10
mΩ
A
µA
Ω
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Push-Pull Current Limit
I
LIM_PP
Current-Limit Autoretry Blanking
Time
Current-Limit Autoretry Off-Time
OPEN-LOAD DETECTION (O_)
Open-Load Pullup Current
Open-Load and Status-Detect
Threshold
Input Logic-High Voltage
Input Logic-Low Voltage
Input Threshold Hysteresis
Input Pulldown/Pullup Resistor
Open-Drain Output Logic-Low
Voltage
Open-Drain Output Leakage
Current
SDO Output Logic-High Voltage
SDO Output Logic-Low Voltage
SDO Pulldown Resistor
t
BLANK
t
RETRY
Push-pull mode, EN = high,
O_ connected to V
DD
or PGND
Push-pull mode, EN = high,
O_ connected to V
DD
or PGND
High-side mode, O_ = off,
0V < V
O_
< (V
DD
– 2V), OL detect = on
EN = high, OL detect = on,
high-side mode, O_ = off
I
OL
V
TOL_
65
6.3
80
7
110
7.7
µA
V
LOGIC INPUTS (IN_, PUSHPL, FLTR, SRIAL, CLK, SDI,
CS,
EN)
V
IH
V
IL
V
ITHYS
R
PULL
(Note 3)
0.7 x V
L
0.3 x V
L
0.1 x
V
L
140
200
270
V
V
V
kΩ
LOGIC OUTPUTS (FAULT,
CERR/IN4,
SDO)
V
ODL
I
LKG_OD
V
OH
V
OL
R
SDO
I
SINK
= 5mA
SRIAL = high, output not asserted,
V
OUT
= 5.5V
I
SOURCE
= 5mA
I
SINK
= 5mA
CS
= high
140
200
-1
V
L
- 0.33
0.33
+1
V
µA
V
0.33
270
V
kΩ
www.maximintegrated.com
Maxim Integrated
│
3
MAX14900E
Octal, High-Speed, Industrial, High-Side Switch
Electrical Characteristics (continued)
(V
DD
= 10V to 36V, V
5
= 4.5V to 5.5V, V
L
= 2.5V to 5.5V, T
A
= -40°C to +125°C, unless otherwise noted. Typical values are at V
DD
= 24V,
V
5
= 5V, V
L
= 3.3V, and T
A
= +25°C.) (Note 2)
PARAMETER
TIMING CHARACTERISTICS
High-Side Mode LTH Output
Propagation Delay
High-side mode, delay from IN_ transition
(parallel mode) or
CS
rising-edge
(serial mode) to O_ rising by 0.5V;
R
L
= 48Ω, C
L
= 1nF, t
R
/t
F
≤ 20ns,
FLTR = low, Figure 1 (Note 4)
High-side mode, delay from IN_ transition
(parallel mode) or
CS
rising-edge
(serial mode) to O_ falling by 0.5V,
R
L
= 48Ω, C
L
= 1nF, t
R
/t
F
≤ 20ns,
FLTR = low, Figure 1 (Note 4)
Push-pull mode, delay from IN_ transition
(parallel mode) or
CS
rising-edge
(serial mode) to O_ settling to within
0.8 x V
DD
, R
L
= 5kΩ, C
L
= 1nF,
FLTR = low, Figure 2
Push-pull mode, delay from IN_ transition
(parallel mode) or
CS
rising-edge
(serial mode) to O_ settling to within
0.2 x V
DD
, R
L
= 5kΩ, C
L
= 1nF,
FLTR = low, Figure 2
High-side mode, 20% to 80%, R
L
= 48Ω,
C
L
= 1nF, Figure 1
Output Rise and Fall Time
t
R
, t
F
Push-pull mode, 20% to 80%, R
L
= 5kΩ,
C
L
= 1nF, Figure 2
Push-pull mode, 20% to 80%, R
L
= 240Ω,
V
CC
= 24V, C
L
= 1nF, Figure 2
Output Switching Rate
Channel-to-Channel Skew
CRC Error-Detect Propagation
Delay
CRC Error-Clear Propagation
Delay
Pulse Length of Rejected Glitch
Admitted Pulse Length
Glitch Filter Propagation
Delay Time
t
PDGF
f
O
t
PDSK_LH
,
t
PDSK_HL
t
PDL_
CERR
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
t
PDHS_LH
0.2
1
µs
High-Side Mode HTL Output
Propagation Delay
t
PDHS_HL
0.9
2
µs
Push-Pull Output LTH
Propagation Delay
t
PDPP_LH
0.3
0.7
µs
Push-Pull Output HTL
Propagation Delay
t
PDPP_HL
0.3
0.8
µs
1.5
0.1
0.1
4
0.4
0.4
100
kHz
ns
µs
Push-pull mode, R
L
= 5kΩ or I
L
= 100mA
to ground, C
L
= 1nF, SRIAL = low
Push-pull mode, Figure 2 (Note 5)
Error detected on SDI data, from
CS
rising-edge to
CERR/IN4
falling-edge;
I
SOURCE
= 5mA, Figure 3
Error cleared, from
CS
rising-edge to
CERR/IN4
rising, I
SOURCE
= 5mA,
Figure 3
FLTR = high
FLTR = high
FLTR = high
0
300
140
-100
+100
14.5
30
ns
t
PDH_CERR
t
GL
17
40
80
ns
ns
ns
300
ns
www.maximintegrated.com
Maxim Integrated
│
4
MAX14900E
Octal, High-Speed, Industrial, High-Side Switch
Electrical Characteristics (continued)
(V
DD
= 10V to 36V, V
5
= 4.5V to 5.5V, V
L
= 2.5V to 5.5V, T
A
= -40°C to +125°C, unless otherwise noted. Typical values are at V
DD
= 24V,
V
5
= 5V, V
L
= 3.3V, and T
A
= +25°C.) (Note 2)
PARAMETER
CLK Clock Period
CLK Pulse-Width High
CLK Pulse-Width Low
CS
Fall-to-CLK Rise Time
SDI Hold Time
SDI Setup Time
Output Data Propagation Delay
SDO Rise and Fall Times
CS
Hold Time
CS
Pulse-Width High
PROTECTION SPECIFICATIONS
Channel Thermal-Shutdown
Threshold
Thermal-Shutdown Hysteresis
Global Thermal-Shutdown
Threshold
Global Thermal-Shutdown
Hysteresis
ESD Protection
Note
Note
Note
Note
2:
3:
4:
5:
T
C_SD
T
C_SD_HYS
T
G_SD
T
G_SD_HYS
V
ESD
O_ pins, Human Body Model (Note 6)
All other pins, Human Body Model
Temperature rising
Temperature rising
+170
15
150
10
±15
±2
°C
°C
°C
°C
kV
SYMBOL
t
CH+CL
t
CH
t
CL
t
CSS
t
DH
t
DS
t
DO
t
FT
t
CSH
t
CSPW
C
L
= 10pF. CLK falling-edge to SDO stable
C
L
= 10pF
(Note 4)
FLTR = low (Note 4)
FLTR = high
50
50
280
4
FLTR = low (Note 4)
FLTR = high
CONDITIONS
MIN
50
5
5
5
300
5
5
25
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SPI TIMING CHARACTERISTICS (Figure 4)
All units are production tested at T
A
= +25°C. Specifications over temperature are guaranteed by design.
All logic input pins except
CS
have a pulldown resistor.
CS
has a pullup resistor.
Specifications are guaranteed by design; not production tested.
Channel-to-channel skew is defined as the difference in propagation delays between channels on the same device with the
same polarity.
Note 6:
Bypass V
DD
pins to AGND with a 1µF capacitor as close as possible to the device for high-ESD protection.
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