Data Sheet
FEATURES
1 pF off capacitance
2.6 pF on capacitance
<1 pC charge injection
33 V supply range
120 Ω on resistance
Fully specified at ±15 V, +12 V
No V
L
supply required
3 V logic-compatible inputs
Rail-to-rail operation
16-lead TSSOP and 16-lead LFCSP
Typical power consumption: <0.03 µW
Low Capacitance, Low Charge Injection,
±15 V/+12 V
iCMOS
Quad SPST Switches
ADG1211/ADG1212/ADG1213
FUNCTIONAL BLOCK DIAGRAM
S1
IN1
D1
S2
IN2
IN2
D2
S3
IN3
D3
S4
IN4
D4
IN4
D4
IN3
D3
S4
IN4
D4
04778-001
S1
IN1
D1
S2
IN2
D2
S3
IN3
IN1
S1
D1
S2
D2
ADG1211
ADG1212
ADG1213
S3
D3
S4
SWITCHES SHOWN FOR A LOGIC 1 INPUT
APPLICATIONS
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Video signal routing
Communication systems
Figure 1.
GENERAL DESCRIPTION
The
ADG1211/ADG1212/ADG1213
are monolithic complemen-
tary metal-oxide semiconductor (CMOS) devices containing
four independently selectable switches designed on an
iCMOS®
(industrial CMOS) process.
iCMOS
is a modular manufacturing
process combining high voltage CMOS and bipolar technologies.
It enables the development of a wide range of high performance
analog ICs capable of 33 V operation in a footprint that no previous
generation of high voltage devices has been able to achieve.
Unlike analog ICs using conventional CMOS processes,
iCMOS
components can tolerate high supply voltages while providing
increased performance, dramatically lower power consumption,
and reduced package size.
The ultralow capacitance and charge injection of these switches
make them ideal solutions for data acquisition and sample-and-
hold applications, where low glitch and fast settling are required.
Fast switching speed coupled with high signal bandwidth make
the devices suitable for video signal switching.
iCMOS
construction ensures ultralow power dissipation,
making the devices ideally suited for portable and battery-
powered instruments.
The
ADG1211/ADG1212/ADG1213
contain four independent
single-pole/single-throw (SPST) switches. The
ADG1211
and
ADG1212
differ only in that the digital control logic is inverted.
The
ADG1211
switches are turned on with Logic 0 on the
appropriate control input, while Logic 1 is required for the
ADG1212.
The
ADG1213
has two switches with digital control
logic similar to that of the
ADG1211;
the logic is inverted on the
other two switches. The
ADG1213
exhibits break-before-make
switching action for use in multiplexer applications.
Each switch conducts equally well in both directions when on
and has an input signal range that extends to the supplies. In the
off condition, signal levels up to the supplies are blocked.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
Ultralow capacitance.
<1 pC charge injection.
3 V logic-compatible digital inputs: V
IH
= 2.0 V, V
IL
= 0.8 V.
No V
L
logic power supply required.
Ultralow power dissipation: <0.03 µW.
16-lead TSSOP and 3 mm × 3 mm LFCSP packages.
Rev. D
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ADG1211/ADG1212/ADG1213
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Dual Supply ................................................................................... 3
Single Supply ................................................................................. 5
Data Sheet
Absolute Maximum Ratings ............................................................6
ESD Caution...................................................................................6
Pin Configurations and Function Descriptions ............................7
Terminology .......................................................................................8
Typical Performance Characteristics ..............................................9
Test Circuits..................................................................................... 12
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 15
REVISION HISTORY
11/2016—Rev. C to Rev. D
Change to VDD Parameter, Table 2 ............................................... 5
3/2016—Rev. B to Rev. C
Changes to Figure 3 .......................................................................... 7
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 15
8/2012—Rev. A to Rev. B
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 5
Change to Table 6 ............................................................................. 7
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 15
2/2009—Rev. 0 to Rev. A
Changes to Power Requirements, I
DD
, Digital Inputs = 5 V
Parameter, Table 1 .............................................................................4
Changes to Power Requirements, I
DD
, Digital Inputs = 5 V
Parameter, Table 2 .............................................................................5
7/2005—Revision 0: Initial Version
Rev. D | Page 2 of 16
Data Sheet
SPECIFICATIONS
DUAL SUPPLY
V
DD
= 15 V ± 10%, V
SS
= −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Y Version
1
−40°C to
+85°C
−40°C to
+125°C
V
DD
to V
SS
120
190
2.5
6
20
57
±0.02
±0.1
±0.02
±0.1
±0.02
±0.1
±0.6
±0.6
±0.6
±1
±1
±1
2.0
0.8
0.005
±0.1
Digital Input Capacitance, C
IN
DYNAMIC CHARACTERISTICS
2
t
ON
t
OFF
Break-Before-Make Time Delay, t
D
(ADG1213 Only)
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise
−3 dB Bandwidth
C
S
(Off )
C
D
(Off )
C
D
, C
S
(On)
2.5
110
130
85
115
25
−0.3
80
90
0.15
1000
0.9
1.1
1
1.2
2.6
3
230
260
ADG1211/ADG1212/ADG1213
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (R
ON
)
On Resistance Match Between
Channels (∆R
ON
)
On Resistance Flatness (R
FLAT(ON)
)
LEAKAGE CURRENTS
Source Off Leakage, I
S
(Off )
Drain Off Leakage, I
D
(Off )
Channel On Leakage, I
D
, I
S
(On)
DIGITAL INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
INL
or I
INH
25°C
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
µA typ
µA max
pF typ
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
% typ
MHz typ
pF typ
pF max
pF typ
pF max
pF typ
pF max
Test Conditions/Comments
V
S
= ±10 V, I
S
= −1 mA; see Figure 20
V
DD
= +13.5 V, V
SS
= −13.5 V
V
S
= ±10 V, I
S
= −1 mA
10
72
11
79
V
S
= −5 V/0 V/+5 V; I
S
= −1 mA
V
DD
= +16.5 V, V
SS
= −16.5 V
V
S
= ±10 V, V
D
=
∓
10 V; see Figure 21
V
S
= ±10 V, V
D
=
∓
10 V; see Figure 21
V
S
= V
D
= ±10 V; see Figure 22
V
IN
= V
INL
or V
INH
160
130
195
150
10
R
L
= 300 Ω, C
L
= 35 pF
V
S
= 10 V; see Figure 23
R
L
= 300 Ω, C
L
= 35 pF
V
S
= 10 V; see Figure 23
R
L
= 300 Ω, C
L
= 35 pF
V
S1
= V
S2
= 10 V; see Figure 24
V
S
= 0 V, R
S
= 0 Ω, C
L
= 1 nF; see Figure 25
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz; see Figure 26
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz; see Figure 27
R
L
= 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz
R
L
= 50 Ω, C
L
= 5 pF; see Figure 28
V
S
= 0 V, f = 1 MHz
V
S
= 0 V, f = 1 MHz
V
S
= 0 V, f = 1 MHz
V
S
= 0 V, f = 1 MHz
V
S
= 0 V, f = 1 MHz
V
S
= 0 V, f = 1 MHz
Rev. D | Page 3 of 16
ADG1211/ADG1212/ADG1213
Parameter
POWER REQUIREMENTS
I
DD
I
DD
I
SS
I
SS
VDD/VSS
1
2
Data Sheet
Y Version
1
−40°C to
+85°C
−40°C to
+125°C
Unit
µA typ
µA max
µA typ
µA max
µA typ
µA max
µA typ
µA max
V min/max
Test Conditions/Comments
V
DD
= +16.5 V, V
SS
= −16.5 V
Digital inputs = 0 V or V
DD
Digital inputs = 5 V
Digital inputs = 0 V or V
DD
Digital inputs = 5 V
25°C
0.001
1.0
220
380
0.001
1.0
0.001
1.0
±4.5/±16.5
Temperature range for Y version is
−40°C
to +125°C.
Guaranteed by design, not subject to production test.
Rev. D | Page 4 of 16
Data Sheet
SINGLE SUPPLY
V
DD
= 12 V ± 10%, V
SS
= 0 V, GND = 0 V, unless otherwise noted.
Table 2.
Y Version
1
−40°C to
+85°C
−40°C to
+125°C
0 V to V
DD
300
475
4.5
12
60
±0.02
±0.1
±0.02
±0.1
±0.02
±0.1
567
625
ADG1211/ADG1212/ADG1213
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (R
ON
)
On Resistance Match Between
Channels (∆R
ON
)
On Resistance Flatness (R
FLAT(ON)
)
LEAKAGE CURRENTS
Source Off Leakage, I
S
(Off )
Drain Off Leakage, I
D
(Off )
Channel On Leakage, I
D
, I
S
(On)
DIGITAL INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
INL
or I
INH
Digital Input Capacitance, C
IN
DYNAMIC CHARACTERISTICS
2
t
ON
t
OFF
Break-Before-Make Time Delay, t
D
(ADG1213 Only)
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
C
S
(Off )
C
D
(Off )
C
D
, C
S
(On)
POWER REQUIREMENTS
I
DD
I
DD
VDD
1
2
25°C
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
µA typ
µA max
pF typ
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
MHz typ
pF typ
pF max
pF typ
pF max
pF typ
pF max
µA typ
µA max
µA typ
µA max
V min/max
Test Conditions/Comments
V
S
= 0 V to 10 V, I
S
= −1 mA; see Figure 20
V
DD
= 10.8 V, V
SS
= 0 V
V
S
= 0 V to 10 V, I
S
= −1 mA
26
27
V
S
= 3 V/6 V/9 V, I
S
= −1 mA
V
DD
= 13.2 V, V
SS
= 0 V
V
S
= 1 V/10 V, V
D
= 10 V/1 V; see Figure 21
V
S
= 1 V/10 V, V
D
= 10 V/1 V; see Figure 21
V
S
= V
D
= 1 V or 10 V; see Figure 22
±0.6
±0.6
±0.6
±1
±1
±1
2.0
0.8
0.001
±0.1
3
130
170
95
120
50
0
80
90
900
1.2
1.4
1.3
1.5
3.2
3.9
0.001
1.0
220
1.0
5/16.5
V
IN
= V
INL
or V
INH
210
145
240
180
10
R
L
= 300 Ω, C
L
= 35 pF
V
S
= 8 V; see Figure 23
R
L
= 300 Ω, C
L
= 35 pF
V
S
= 8 V; see Figure 23
R
L
= 300 Ω, C
L
= 35 pF
V
S1
= V
S2
= 8 V; see Figure 24
V
S
= 6 V, R
S
= 0 Ω, C
L
= 1 nF; see Figure 25
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz; see Figure 26
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz; see Figure 27
R
L
= 50 Ω, C
L
= 5 pF; see Figure 28
V
S
= 6 V, f = 1 MHz
V
S
= 6 V, f = 1 MHz
V
S
= 6 V, f = 1 MHz
V
S
= 6 V, f = 1 MHz
V
S
= 6 V, f = 1 MHz
V
S
= 6 V, f = 1 MHz
V
DD
= 13.2 V
Digital inputs = 0 V or V
DD
Digital inputs = 5 V
V
SS
= 0 V, GND = 0 V
Temperature range for Y version is
−40°C
to +125°C.
Guaranteed by design, not subject to production test.
Rev. D | Page 5 of 16
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