74VHC02MTCX_NL datasheet, PDF - EEWORLD Datasheet

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74VHC02MTCX_NL: DescriptionLogic Gates FINISHED GOOD; Categorylogic logic; File Size281KB，9 Pages; ManufacturerFairchild; Websitehttp://www.fairchildsemi.com/; Environmental Compliance

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74VHC02MTCX_NL Overview

Logic Gates FINISHED GOOD

74VHC02MTCX_NL Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Fairchild
Parts packaging code	TSSOP
package instruction	TSSOP, TSSOP14,.25
Contacts	14
Reach Compliance Code	compliant
series	AHC/VHC
JESD-30 code	R-PDSO-G14
JESD-609 code	e3
length	5 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	NOR GATE
MaximumI(ol)	0.008 A
Humidity sensitivity level	1
Number of functions	4
Number of entries	2
Number of terminals	14
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP14,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260
power supply	2/5.5 V
Prop。Delay @ Nom-Sup	8.5 ns
propagation delay (tpd)	13 ns
Certification status	Not Qualified
Schmitt trigger	NO
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	4.4 mm
Base Number Matches	1

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74VHC02 — Quad 2-Input NOR Gate

December 2007

74VHC02

Quad 2-Input NOR Gate

Features

■

High Speed: t

3.6ns (Typ.) at V

■

Low power dissipation: I

2µA (Max.) at T

25°C

■

High noise immunity: V

NIH

NIL

28% V

(Min.)

■

Power down protection is provided on all inputs

■

Low noise: V

OLP

0.8V (Max.)

■

Pin and function compatible with 74HC02

General Description

The VHC02 is an advanced high-speed CMOS 2-Input

NOR Gate fabricated with silicon gate CMOS technol-

ogy. It achieves the high-speed operation similar to

equivalent Bipolar Schottky TTL while maintaining the

CMOS low power dissipation. The internal circuit is

composed of 3 stages, including buffer output, which

provide high noise immunity and stable output. An input

protection circuit insures that 0V to 7V can be applied to

the input pins without regard to the supply voltage. This

device can be used to interface 5V to 3V systems and

two supply systems such as battery backup. This circuit

prevents device destruction due to mismatched supply

and input voltages.

Ordering Information

Order Number

74VHC02M

74VHC02SJ

74VHC02MTC

Package

Number

M14A

M14D

MTC14

Package Description

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"

Narrow

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

4.4mm Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

74VHC02 Rev. 1.4.0

www.fairchildsemi.com

74VHC02MTCX_NL Related Products

	74VHC02MTCX_NL	74VHC02N_Q
Description	Logic Gates FINISHED GOOD	Logic Gates Qd 2-Input NOR Gate

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