®
®
ADC-305
8-Bit, 20MHz CMOS A/D Converters
OBSOLETE PRODUCT
PRODUCT OVERVIEW
Contact Factory for Replacement Model
and a wide 18MHz (–1dB)
DATEL's ADC-305 is an 8-bit, 20MHz sam-
sipation (60mW typical)
input signal bandwidth.
The ADC-305-1 is packaged in 400 mil 24-pin DIP
and the ADC-305-3 in 300 mil 24-pin SOP.
Other features are CMOS compatible input logic,
3-state TTL compatible output logic, +5V single
power operation, self bias mode and low cost.
FUNCTION
DGND
REF. BOTTOM (VRB)
SELF BIAS 1 (VRBS)
AGND
AGND
ANALOG INPUT (VIN)
+AVS (+5V)
REFERENCE TOP (VRT)
SELF BIAS 2 (VRTS)
+AVS (+5V)
+AVS (+5V)
+DVS (+5V)
pling, CMOS, subranging (two-pass) A/D converter.
It processes signals at speeds comparable to a full
flash converter by using a sub-ranging conversion
technique with multiple comparator blocks, each
containing a sample and hold amplifier.
The ADC-305 features CMOS low power dis-
Pin
1
2
3
4
5
6
7
8
9
10
11
12
FEATURES
■
■
■
■
■
■
■
INPUT/OUTPUT CONNECTIONS
FUNCTION
Pin
OUTPUT ENABLE (OE)
24
DGND
BIT 8 (LSB)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1 (MSB)
+DVS (+5V)
CLOCK INPUT (A/D CLK)
23
22
21
20
19
18
17
16
15
14
13
8-bit resolution, 20MHz min. sampling rate
±½LSB max. differential nonlinearity error
18MHz input signal bandwidth
Subranging, S&H enclosed
+5V single power, low 85mW max. dissipation
CMOS compatible logic input
3-State TTL compatible output
Both the ADC-305-1 and the ADC-305-3 have the same pin assignment.
OUTPUT ENABLE 1
DGND 2
BIT 8 (LSB) 3
BIT 7 4
BIT 6 5
BIT 5 6
BIT 4 7
BIT 3 8
BIT 2 9
BIT 1 (MSB) 10
+DV
S
11
A/D CLK 12
CLOCK
GENERATOR
UPPER
DATA
LATCHES
LOWER
ENCODER
(4 BIT)
A BLOCK
COMPARATORS
WITH S/H (4 BIT)
LOWER
DATA
LATCHES
LOWER
ENCODER
(4 BIT)
B BLOCK
COMPARATORS
WITH S/H (4 BIT)
REFERENCE
VOLTAGE
24 DGND
23 V
RB
22 V
RBS
21 AGND
20 AGND
19 V
IN
18 +AV
S
17 V
RT
UPPER
ENCODER
(4 BIT)
UPPER
COMPARATORS
WITH S/H (4 BIT)
16 V
RTS
15 +AV
S
14 +AV
S
13 +DV
S
Figure 1. Functional Block Diagram
DATEL
•
11 Cabot Boulevard, Mansfield, MA 02048-1151 USA •
Tel: (508) 339-3000
•
www.datel.com
•
e-mail: help@datel.com
30 Mar 2011
MDA_ADC-305.B02
Page 1 of 6
®
®
ADC-305
8-Bit, 20MHz CMOS A/D Converters
MAX
+7
+AVS +0.5
+AVS +0.5
+DVS +0.5
+DVS +0.5
UNITS
Volts
Volts
Volts
Volts
Volts
POWER REQUIREMENTS
Power Supply
(+AV
S
, +DV
S
)
I A GND - D GND I
Power Supply Current
Power Dissipation
Min.
+4.75
—
—
—
Typ.
+5.0
—
12
60
Max.
+5.25
100
17
85
Units
Volts
mV
mA
mW
PARAMETERS
Power Supply Voltage (+AVS, +DVS)
Analog Input Voltage (VIN)
Reference Input Voltage (VRT, VRB)
Digital Input Voltage (VIH, VIL)
Digital Output Voltage (VOH, VOL)
MIN
–0.5
–0.5
–0.5
–0.5
–0.5
Functional Specifications
Analog Inputs
Input Voltage Range
(V
IN
)
➀
Input Capacitance
(V
IN
= 1.5Vdc+0.07V
RMS
)
Input Impedance
Input Signal Bandwidth
(V
IN
-2Vp-p, –1dB)
Ref. Resitance
Ref. Current
Ref. Voltage
➀
V
RT
to V
RB
(Specification are typical at T
A
= +25°C, +V
RT
= +2.5V, V
RB
= +0.5V, +AV
S
= +DV
S
=
+5v, f
S
= 20MHz sampling unless otherwise specified.)
Min.
—
—
—
—
REFERENCE INPUTS
230
4.5
+1.8
0
–10
0
+0.6
+1.96
+2.25
DIGITAL INPUTS
Input Voltage
(CMOS)
Logic Levels (V
IH
) "1"
Logic Level (V
IL
) "0"
Input Current
(@V
IH
=+DV
S
)"1"
(@V
IL
=0) "0"
Clock Pulse Width
T
PW1
(A/D CLK)
T
PW0
Output Data
Output Voltage
Output Current
➃
Logic Level "1"
Logic Level "0"
Output Current
➄
Logic Level "1"
Logic Level "0"
Output Data Delay,
Td
Resolution
Maximum Sampling Rate
Minimum Sampling Rate
Aperature Delay,
T
A
Aperature Jitter
Differential Linearity Error
Integral Linearity Error
Differential Gain Error
➅
Differential Phase Error
➅
+4
—
—
—
25
25
DIGITAL Outputs
8-bit Binary Parallel
3-State TTL compatible
–1.1
+3.7
—
—
—
PERFORMANCE
8
20
—
—
—
—
—
—
—
—
—
—
—
18
—
—
—
4
30
±0.3
+0.5
1
0.5
—
—
16
16
30
—
—
0.5
—
—
±0.5
+1.3
—
—
mA
mA
μA
μA
ns
Bit
MHz
MHz
ns
ps
LSB
LSB
%
deg
b.
Typ.
Max.
+0.5 to +2.5
—
11
—
12.5
18
—
—
Units
Volts
pF
kΩ
MHz
Physical/Environmental
Operating Temp. Range
–40 to +85°C
Storage Temp. Range
–55 to +150°C
Package Type
ADC-305-1
24-pin Plastic DIP
ADC-305-3
24-pin Plastic SOP
Weight
ADC-305-1
2.0 grams
ADC-305-3
0.3 grams
Technical Notes
1.
The ADC-305 has separate +AVS and +DVS pins. It is recommended that both +AVS
and +DVS be powered from a single supply since a time lag between start up of separate
supplies could induce latch up. Other external logic circuits must be powered from a separate
digital supply. +DVS (pins 11 and 13) and +AVs (pins 14, 15 and 18) should be tied together
externally. DGND (pins 2 and 24) and AGND (pins 20 and 21) should also be tied together
externally. Power supply grounds must be connected at one point to the ground plane directly
beneath the device. Digital returns should not flow through analog grounds.
Bypass all power lines to ground with a 0.1μF ceramic chip capacitor in parallel with a 47μF
electrolytic capacitor. Locate the bypass capacitor as close to the unit as possible.
Even though the analog input capacitance is a low 15pF, it is recommended that high
frequency input be provided via a high speed buffer amplifier. A parasitic oscillation may be
generated when a high speed amplifier is used. A 75 ohm resister inserted between the output
of an amplifier and the analog input of the ADC-305 will improve the situation. A resistor larger
than 100 ohms may degrade linearity.
The input voltage range is determined by voltages applied to VRB (Reference Bottom) and
VRT (Reference Top). Keep to the following equations:
0V≤VRB≤VRT≤2.8V
1.8V≤VRT–VRB≤2.8V
The analog input range is normally 2Vp-p.
Self Bias Mode
a.
Tie VRB to VRBS, and tie VRT to VRTS respectively. The analog input range in this case is
+0.64V to +2.73V nominal.
Tie VRB to AGND, and tie VRT to VRTS respectively. The analog input voltage range is 0 to
+2.39V in this case. These values may differ from one device to another. Voltage changes on
the +5V supply have a direct influence on the performance of the device. The use of external
references is recommended for applications sensitive to gain error.
V
RT
V
RB
Offset Voltage
V
RT
V
RB
Self Bias I
➀ ➁
V
RBS
V
RTS
-V
RBS
Self Bias II
➀ ➂
V
RTS
300
6.6
—
—
–35
+15
+0.64
+2.09
+2.39
450
8.7
+2.8
V
RT
–60
+45
+0.68
+2.21
+2.53
Ω
mA
Volts
Volts
mV
mV
Volts
Volts
Volts
2.
3.
4.
—
—
—
—
—
—
—
+1
5
5
—
—
Volts
Volts
μA
μA
ns
ns
External Reference Mode
Tie VRB to AGND, and apply +2V to VRT to use at 0 to +2V input voltage range. The reference
resistance between VRB and VRT is about 300 ohms. It is important to make the output
impedance of the reference source small enough while, at the same time, keeping sufficient
drive capacity. Insert a 0.1μF bypass ceramic chip capacitor between VRT and GND to
minimize the effect of the 20MHz clock running nearby. See Figure 5.
5.
6.
Logic inputs are CMOS compatible. Normally a series 74HC is used as a driver. It is
recommended to pull up to +5V if the device is driven with TTL.
The start convert (A/D CLK) pulse can be a 50% duty cycle clock. Both TPW1 and TPW0 are
25ns minimum. A slightly longer TPW1 will improve linearity of the system for higher frequency
input signals.
7. The digital data outputs are 3-state and TTL compatible. To enable the 3-state
outputs, connect the OUTPUT ENABLE (pin 1) to GND. To disable, connect it to
+5V. It is recommended that the data outputs be latched and buffered through
output registers.
8. Maximum 30ns (18ns typical) after the rising edge of the Nth conversion pulse, the
result of the (N-3) conversion can be obtained. Data is stored firmly in an output
register, such as an 74LS574, using the rising edge of a start convert pulse as a
trigger. The (N–4) data is stored in this case. See the timing diagrams, Figure 2
and 4.
9. The 20MHz sampling rate is guaranteed. It is not recommended to use this device
at sampling rates slower than 500kHz because the droop characteristics of the
internal sample and holds will then exceed the limit required to maintain the
specified accuracy of the device.
Tel: (508) 339-3000
•
www.datel.com
•
e-mail: help@datel.com
Footnotes:
➀
See Technical Note 4
➁
Short V
RB
(pin 23) to V
RBS
(pin 22).
Short V
RT
(pin 17) to V
RTS
(pin 16).
➂
Short V
RB
(pin 23) to A GND.
Short V
RT
(pin 17) to V
RTS
(pin 16).
➃
OE=OV, V
OH
=+DV
S
–0.5V,
V
OL
=+0.4V
➄
OE=+DV
S
, V
OH
=+DV
S
, V
OL
=0V
➅
NTSC 40IRE mode ramp, 14.3MHz
sampling
DATEL
•
11 Cabot Boulevard, Mansfield, MA 02048-1151 USA •
30 Mar 2011
MDA_ADC-305.B02
Page 2 of 6
Embedded System
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