Programmable Clock Generator
5P49V5944
DATASHEET
Description
The 5P49V5944 is a programmable clock generator intended
for high-performance consumer, networking, industrial,
computing, and data-communications applications.
Configurations may be stored in on-chip One-Time
Programmable (OTP) memory or changed using I
2
C
interface. This is IDT’s fifth generation of programmable clock
technology (VersaClock
®
5).
The frequencies are generated from a single reference clock.
The input reference can be either a crystal or an LVCMOS
reference clock.
Two select pins allow up to 4 different configurations to be
programmed and accessible using processor GPIOs or
bootstrapping. The different selections may be used for
different operating modes (full function, partial function, partial
power-down), regional standards (US, Japan, Europe) or
system production margin testing.
The device may be configured to use one of two I
2
C
addresses to allow multiple devices to be used in a system.
Features
•
Generates up to two independent output frequencies
•
High-performance, low phase noise PLL, < 0.7ps RMS
typical phase jitter on outputs:
– PCIe Gen1–3 compliant clock capability
– USB 3.0 compliant clock capability
– 1 GbE and 10 GbE
•
Two fractional output dividers (FODs)
•
Independent spread spectrum capability on each output
pair
•
Four banks of internal non-volatile in-system
programmable or factory programmable OTP memory
•
I
2
C serial programming interface
•
One reference LVCMOS output clock
•
Two universal output pairs:
– Each configurable as one differential output pair or two
LVCMOS outputs
I/O standards:
– Single-ended I/Os: 1.8V to 3.3V LVCMOS
– Differential I/Os: LVPECL, LVDS and HCSL
•
Pin Assignment
OUT0_SEL_I2CB
•
Input frequency ranges:
V
DDO
0
– LVCMOS reference clock input (XIN/REF): 1MHz to
200MHz
– Crystal frequency range: 8MHz to 40MHz
Output frequency ranges:
– LVCMOS clock outputs: 1MHz to 200MHz
– LVDS, LVPECL, HCSL differential clock outputs: 1MHz
to 350MHz
GND
GND
V
DDD
•
V
DDO
1
OUT1
OUT1B
GND
GND
XOUT
XIN/REF
V
DDA
GND
SD/OE
1
2
3
4
5
20 19 18 17 16
15
14
•
Individually selectable output voltage (1.8V, 2.5V, 3.3V) for
each output pair
EPAD
13
12
6
7
8
9
11
10
3 × 3 mm 20-VFQFPN
•
•
•
•
•
•
•
•
•
Programmable loop bandwidth
Programmable output to output skew
Programmable slew rate control
Programmable crystal load capacitance
Individual output enable/disable
Power-down mode
1.8V, 2.5V or 3.3V core V
DDD
, V
DDA
3 x 3 mm 20-VFQFPN package
-40° to +85°C industrial temperature operation
SEL1/SDA
SEL0/SCL
V
DDO
2
OUT2
5P49V5944 OCTOBER 30, 2017
OUT2B
1
©2017 Integrated Device Technology, Inc.
5P49V5944 DATASHEET
Functional Block Diagram
V
DDO
0
XIN/REF
XOUT
SD/OE
SEL1/SDA
SEL0/SCL
V
DDA
V
DDD
FOD2
OUT2B
OTP
and
Control Logic
OUT0_SEL_I2CB
V
DDO
1
PLL
OUT1
FOD1
OUT1B
V
DDO
2
OUT2
Applications
•
•
•
•
•
•
•
•
•
•
Ethernet switch/router
PCI Express 1.0/2.0/3.0
Broadcast video/audio timing
Multi-function printer
Processor and FPGA clocking
Any-frequency clock conversion
MSAN/DSLAM/PON
Fiber channel, SAN
Telecom line cards
1 GbE and 10 GbE
PROGRAMMABLE CLOCK GENERATOR
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OCTOBER 30, 2017
5P49V5944 DATASHEET
Table 1: Pin Descriptions
Number
1
2
3
4
Name
XOUT
XIN/REF
VDDA
GND
Type
Input
Input
Power
Power
Description
Crystal Oscillator interface output.
Crystal Oscillator interface input, or single-ended LVCMOS clock input. Ensure
that the input voltage is 1.2V max. Refer to the section “Overdriving the XIN/REF
Interface”.
Analog functions power supply pin. Connect to 1.8V to 3.3V. VDDA and VDDD
should have the same voltage applied.
Connect to ground.
Enables/disables the outputs (OE) or powers down the chip (SD). The SH bit
controls the configuration of the SD/OE pin. The SH bit needs to be high for
SD/OE pin to be configured as SD. The SP bit (0x02) controls the polarity of the
signal to be either active HIGH or LOW only when pin is configured as OE
(Default is active LOW.) Weak internal pull down resistor. When configured as
SD, device is shut down, differential outputs are driven high/low, and the single-
ended LVCMOS outputs are driven low. When configured as OE, and outputs are
disabled, the outputs can be selected to be tri-stated or driven high/low,
depending on the programming bits as shown in the SD/OE Pin Function Truth
table.
Configuration select pin, or I2C SDA input as selected by OUT0_SEL_I2CB.
Weak internal pull down resistor.
Configuration select pin, or I2C SCL input as selected by OUT0_SEL_I2CB.
Weak internal pull down resistor.
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for
OUT2/OUT2B.
Output Clock 2. Please refer to the Output Drivers section for more details.
Complementary Output Clock 2. Please refer to the Output Drivers section for
more details.
Connect to ground.
Connect to ground.
Complementary Output Clock 1. Please refer to the Output Drivers section for
more details.
Output Clock 1. Please refer to the Output Drivers section for more details.
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for
OUT1/OUT1B.
Connect to ground.
Digital functions power supply pin. Connect to 1.8 to 3.3V. VDDA and VDDB
should have the same voltage applied.
Connect to ground.
Power supply pin for OUT0_SEL_I2CB. Connect to 1.8 to 3.3V. Sets output
voltage levels for OUT0.
Latched input/LVCMOS Output. At power up, the voltage at the pin
OUT0_SEL_I2CB is latched by the part and used to select the state of pins 8
and 9. If a weak pull up (10Kohms) is placed on OUT0_SEL_I2CB, pins 8 and 9
will be configured as hardware select pins, SEL1 and SEL0. If a weak pull down
(10Kohms) is placed on OUT0_SEL_I2CB or it is left floating, pins 8 and 9 will
act as the SDA and SCL pins of an I2C interface. After power up, the pin acts as
a LVCMOS reference output.
Connect to ground pad.
5
SD/OE
Input
Pull-down
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SEL1/SDA
SEL0/SCL
VDDO2
OUT2
OUT2B
GND
GND
OUT1B
OUT1
VDDO1
GND
VDDD
GND
VDDO0
Input
Input
Power
Output
Output
Power
Power
Output
Output
Power
Power
Power
Power
Power
Pull-down
Pull-down
20
OUT0_SELB_I2C Input/Output
Pull-down
ePAD
OCTOBER 30, 2017
3
PROGRAMMABLE CLOCK GENERATOR
5P49V5944 DATASHEET
PLL Features and Descriptions
Spread Spectrum
To help reduce electromagnetic interference (EMI), the
5P49V5944 supports spread spectrum modulation. The
output clock frequencies can be modulated to spread energy
across a broader range of frequencies, lowering system EMI.
The 5P49V5944 implements spread spectrum using the
Fractional-N output divide, to achieve controllable modulation
rate and spreading magnitude. The spread spectrum can be
applied to any output clock, any clock frequency, and any
spread amount from ±0.25% to ±2.5% center spread and
-0.5% to -5% down spread.
After a pin level change, the device must not be interrupted for
at least 1ms so that the new values have time to load and take
effect.
If OUT0_SEL_I2CB was 0 at POR, alternate configurations
can only be loaded via the I
2
C interface.
Table 2:
Loop Filter
PLL loop bandwidth range depends on the input reference
frequency (Fref) and can be set between the loop bandwidth
range as shown in the table below.
Input Reference
Loop
Loop
Frequency–Fref Bandwidth Min Bandwidth Max
(MHz)
(kHz)
(kHz)
1
350
40
300
126
1000
Table 3:
Configuration Table
This table shows the SEL1, SEL0 settings to select the
configuration stored in OTP. Four configurations can be stored
in OTP. These can be factory programmed or user
programmed.
OUT0_SEL_I2CB SEL1 SEL0
I
2
C
REG0:7 Config
at POR
Access
1
1
1
1
0
0
0
0
1
1
X
X
0
1
0
1
X
X
No
No
No
No
Yes
Yes
0
0
0
0
1
0
0
1
2
3
I
2
C
defaults
0
At power up time, the SEL0 and SEL1 pins must be tied to
either the VDDD/VDDA power supply so that they ramp with
that supply or are tied low (this is the same as floating the
pins). This will cause the register configuration to be loaded
that is selected according to Table 3 above. Providing that
OUT0_SEL_I2CB was 1 at POR and OTP register 0:7 = 0,
after the first 10ms of operation the levels of the SELx pins can
be changed, either to low or to the same level as
VDDD/VDDA. The SELx pins must be driven with a digital
signal of < 300ns Rise/Fall time and only a single pin can be
changed at a time.
PROGRAMMABLE CLOCK GENERATOR
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OCTOBER 30, 2017
5P49V5944 DATASHEET
Reference Clock Input Pins
The 5P49V5944 supports one clock input. The clock input
(XIN/ REF) can be driven by either an external crystal or a
reference clock.
Crystal Input (XIN/REF)
The crystal used should be a fundamental mode quartz
crystal; overtone crystals should not be used.
A crystal manufacturer will calibrate its crystals to the nominal
frequency with a certain load capacitance value. When the
oscillator load capacitance matches the crystal load
capacitance, the oscillation frequency will be accurate. When
the oscillator load capacitance is lower than the crystal load
capacitance, the oscillation frequency will be higher than
nominal and vice versa so for an accurate oscillation
frequency you need to make sure to match the oscillator load
capacitance with the crystal load capacitance.
To set the oscillator load capacitance there are two tuning
capacitors in the IC, one at XIN and one at XOUT. They can
be adjusted independently but commonly the same value is
used for both capacitors. The value of each capacitor is
composed of a fixed capacitance amount plus a variable
capacitance amount set with the XTAL[5:0] register.
Adjustment of the crystal tuning capacitors allows for
maximum flexibility to accommodate crystals from various
manufacturers. The range of tuning capacitor values available
are in accordance with the following table.
You can write the following equations for the total capacitance
at each crystal pin:
C
XIN
= Ci
1
+ Cs
1
+ Ce
1
C
XOUT
= Ci
2
+ Cs
2
+ Ce
2
Ci
1
and Ci
2
are the internal, tunable capacitors. Cs
1
and Cs
2
are stray capacitances at each crystal pin and typical values
are between 1pF and 3pF.
Ce
1
and Ce
2
are additional external capacitors that can be
added to increase the crystal load capacitance beyond the
tuning range of the internal capacitors. However, increasing
the load capacitance reduces the oscillator gain so please
consult the factory when adding Ce
1
and/or Ce
2
to avoid
crystal startup issues. Ce
1
and Ce
2
can also be used to adjust
for unpredictable stray capacitance in the PCB.
The final load capacitance of the crystal:
C
L
= C
XIN
× C
XOUT
/ (C
XIN
+ C
XOUT
)
For most cases it is recommended to set the value for
capacitors the same at each crystal pin:
C
XIN
= C
XOUT
= Cx
→
C
L
= Cx / 2
The complete formula when the capacitance at both crystal
pins is the same:
C
L
= (9pF + 0.5pF × XTAL[5:0] + Cs + Ce) / 2
Example 1:
The crystal load capacitance is specified as 8pF
and the stray capacitance at each crystal pin is Cs = 1.5pF.
Assuming equal capacitance value at XIN and XOUT, the
equation is as follows:
8pF = (9pF + 0.5pF × XTAL[5:0] + 1.5pF) / 2
→
0.5pF × XTAL[5:0] = 5.5pF
→
XTAL[5:0] = 11 (decimal)
Example 2:
The crystal load capacitance is specified as 12pF
and the stray capacitance Cs is unknown. Footprints for
external capacitors Ce are added and a worst case Cs of 5pF
is used. For now we use Cs + Ce = 5pF and the right value for
Ce can be determined later to make 5pF together with Cs.
12pF = (9pF + 0.5pF × XTAL[5:0] + 5pF) / 2
→
XTAL[5:0] = 20 (decimal)
XTAL[5:0] Tuning Capacitor Characteristics
Parameter
XTAL
Bits
6
Step (pF)
0.5
Min. (pF)
9
Max. (pF)
25
The capacitance at each crystal pin inside the chip starts at
9pF with setting 000000b and can be increased up to 25pF
with setting 111111b. The step per bit is 0.5pF.
You can write the following equation for this capacitance:
Ci = 9pF + 0.5pF × XTAL[5:0]
The PCB where the IC and the crystal will be assembled adds
some stray capacitance to each crystal pin and more
capacitance can be added to each crystal pin with additional
external capacitors.
OCTOBER 30, 2017
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PROGRAMMABLE CLOCK GENERATOR
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