Operating Free-Air Temperature Range, TA . . . . . . −40°C to 85°C
Lead Temperature 1.6mm (1/16″ from case for 10s) . . . . . . 220°C
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not supported.
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT PREVIEW
ADS5272
HTQFP-80(2)
PFP
−40°C to +85°C
ADS5272IPFP
ADS5272IPFP
Tray, 96
″
″
″
″
″
ADS5272IPFPT
Tape and Reel, 250
(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.
(2) Thermal pad size: 4.69mm x 4.69mm (min), 6.20mm x 6.20mm (max).
RELATED PRODUCTS
MODEL
ADS5270
ADS5271
ADS5273
ADS5275
ADS5276
ADS5277
RESOLUTION (BITS)
12
12
12
10
10
10
SAMPLE RATE (MSPS)
40
50
70
40
50
65
CHANNELS
8
8
8
8
8
8
RECOMMENDED OPERATING CONDITIONS
ADS5272
MIN
SUPPLIES AND REFERENCES
Analog Supply Voltage, AVDD
Output Driver Supply Voltage, LVDD
CLOCK INPUT AND OUTPUTS
ADCLK Input Sample Rate (low-voltage TTL)
Low Level Voltage Clock Input
High Level Voltage Clock Input
ADCLKP and ADCLKN Outputs (LVDS)
LCLKP and LCLKN Outputs (LVDS)(1)
Operating Free-Air Temperature, TA
Thermal Characteristics
q
JA
q
JC
(1) 6
×
ADCLK.
3.0
3.0
20
VDD − 0.6
20
120
−40
21
68
TYP
3.3
3.3
MAX
3.6
3.6
65
0.6
65
390
+85
UNIT
V
V
MSPS
V
V
MHz
MHz
°C
°C/W
°C/W
REFERENCE SELECTION
MODE
2.0VPP Internal Reference
External Reference
2
INT/EXT
1
0
DESCRIPTION
Default with internal pull-up.
Internal reference is powered down. Common mode of external reference should be within
50mV of VCM. VCM is derived from the internal bandgap voltage.
ADS5272
www.ti.com
SBAS324 − JUNE 2004
ELECTRICAL CHARACTERISTICS
TMIN = −40°C, and TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V,
LVDD = 3.3V, −1dBFS, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted.
ADS5272
PARAMETER
DC ACCURACY
No Missing Codes
DNL
INL
Differential Nonlinearity
Integral Nonlinearity
Offset
Error
(1)
Offset Temperature Coefficient
Fixed Attenuation in Channel
(2)
Variable Attenuation in
Gain
POWER SUPPLY
I
CC
I(AVDD)
I(LVDD)
Total Supply Current
Analog Supply Current
Digital Output Driver Supply Current
Power Dissipation
Power Down
REFERENCE VOLTAGES
VREF
T
VREF
B
V
CM
VREF
T
VREF
B
ANALOG INPUT
Differential Input Capacitance
Analog Input Common-Mode Range
Differential Input Voltage Range
Voltage Overload Recovery Time
Input Bandwidth
DIGITAL DATA OUTPUTS
Data Bit Rate
SERIAL INTERFACE
SCLK
V
IN
LOW
V
IN
HIGH
Serial Clock Input Frequency
Input Low Voltage
Input High Voltage
Input Current
Input Pin Capacitance
(1)
(2)
TEST CONDITIONS
MIN
TYP
Assured
MAX
UNITS
f
IN
= 5MHz
f
IN
= 5MHz
−0.9
−2.0
TBD
±0.5
±0.6
±0.2
14
1
±0.2
0.9
2.0
TBD
LSB
LSB
%FS
ppm/°C
%FS
%FS
Channel
(3)
REF
T
− REF
B
TBD
Error
(4)
±1.0
44
TBD
%FS
ppm/°C
mA
mA
mA
Gain Temperature Coefficient
(5)
V
IN
= FS, F
IN
= 5MHz
V
IN
= FS, F
IN
= 5MHz
V
IN
= FS, F
IN
= 5MHz, LVDS Into 100Ω Load
Clock Running
1.95
0.95
1.45
±50mV
Change in Voltage
1.875
302
TBD
TBD
996
90
2.0
1.0
1.5
±2
1.125
2.0
2.05
1.05
1.55
TBD
mW
Reference Top (internal)
Reference Bottom (internal)
Common-Mode Voltage
V
CM
Output
Current
(6)
Reference Top (external)
Reference Bottom (external)
External Reference Input
Current
(7)
V
V
V
mA
V
V
mA
7.0
V
CM
±
0.05
1.5
Differential Input Signal at 4V
PP
Recovery to Within 1% of Code
−3dBFS
4.0
300
2.02
pF
V
V
PP
CLK Cycles
MHz
340
780
20
MBPS
MHz
V
V
µA
pF
0
2.1
±10
5.0
0.6
VDD
(3)
(4)
(5)
(6)
(7)
Offset error is the deviation of the average code from mid-code for a zero input. Offset error is expressed in terms of % of full-scale.
Fixed attenuation in the channel arises due to a fixed attenuation of about 1% in the sample-and-hold amplifier. When the differential voltage at the analog input pins are
changed from −V
REF
to +V
REF
, the swing of the output code is expected to deviate from the full-scale code (4096LSB) by the extent of this fixed attenuation [V
REF
is defined
as (REF
T
− REF
B
)].
Variable attenuation in the channel refers to the attenuation of the signal in the channel over and above the fixed attenuation.
The reference voltages are trimmed at production so that (VREF
T
− VREF
B
) is within
±
25mV of the ideal value of 1V. It does not include fixed attenuation.
The gain temperature coefficient refers to the temperature coefficient of the attenuation in the channel. It does not account for the variation of the reference voltages with
temperature.
V
CM
provides the common-mode current for the inputs of all eight channels when the inputs are AC-coupled. The V
CM
output current specified is the additional drive of
the V
CM
buffer if loaded externally.
Average current drawn from the reference pins in the external reference mode.
3
PRODUCT PREVIEW
mW
ADS5272
www.ti.com
SBAS324 − JUNE 2004
AC CHARACTERISTICS
TMIN = −40°C, TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V,
−1dBFS, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted.
ADS5272
PARAMETER
DYNAMIC CHARACTERISTICS
fIN = 1MHz
fIN = 5MHz
fIN = 10MHz
fIN = 20MHz
fIN = 1MHz
fIN = 5MHz
fIN = 10MHz
fIN = 20MHz
fIN = 1MHz
fIN = 5MHz
fIN = 10MHz
fIN = 20MHz
fIN = 1MHz
fIN = 5MHz
fIN = 10MHz
fIN = 20MHz
fIN = 1MHz
fIN = 5MHz
fIN = 10MHz
fIN = 20MHz
f1 = 9.5MHz at −7dBFS
f2 = 10.2MHz at −7dBFS
fIN = 5MHz
Signal Applied to 7 Channels;
Measurement Taken on the Channel with
No Input Signal
TBD
87
85
85
83
90
90
89
86
87
85
85
83
70.5
70.5
70.5
70.5
70
70
70
70
−85
11.3
−90
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
dBc
CONDITIONS
MIN
TYP
MAX
UNITS
SFDR
Spurious-Free Dynamic Range
HD2
2nd-Order Harmonic Distortion
TBD
HD3
3rd-Order Harmonic Distortion
TBD
SNR
Signal-to-Noise Ratio
TBD
PRODUCT PREVIEW
SINAD
Signal-to-Noise and Distortion
TBD
IMD
ENOB
Crosstalk
Two-Tone Intermodulation Distortion
Effective Number of Bits
LVDS DIGITAL DATA AND CLOCK OUTPUTS
Test conditions at IO = 3.5mA, RLOAD = 100Ω, and CLOAD = 9pF. IO refers to the current setting for the LVDS buffer. RLOAD is the differential load resistance
between the differential LVDS pair. CLOAD is the effective single-ended load capacitance between the differential LVDS pins and ground. CLOAD includes the
receiver input parasitics as well as the routing parasitics. Measurements are done with a transmission line of 100Ω differential impedance between the device and
the load. All LVDS specifications are functionally tested, but not parametrically tested.
PARAMETER
DC SPECIFICATIONS(1)
VOH
VOL
VOD
VOS
CO
∆V
OD
∆V
OS
ISOUT
Output Voltage High, OUTP or OUTN
Output Voltage Low, OUTP or OUTN
Output Differential Voltage,
OUTP − OUTN
Output Offset Voltage(2)
Output Capacitance(3)
Change in
VOD
Between 0 and 1
Change Between 0 and 1
Output Short-Circuit Current
CONDITIONS
RLOAD = 100Ω
±
1%; See LVDS Timing Diagram, Page 7
RLOAD = 100Ω
±
1%
RLOAD = 100Ω
±
1%
RLOAD = 100Ω
±
1%; See LVDS Timing Diagram, Page 7
VCM = 1.5V
RLOAD = 100Ω
±
1%
RLOAD = 100Ω
±
1%
Drivers Shorted to Ground
Drivers Shorted Together
6
×
ADCLK
45
50
650
650
IO = 2.5mA
IO = 3.5mA
IO = 4.5mA
IO = 6mA
(1)
(2)
(3)
(4)
(5)
400
250
200
150
ps
ps
ps
MIN
TYP
1375
900
300
1100
1025
350
1200
4
25
25
40
12
55
400
1300
MAX
1500
UNITS
mV
mV
mV
mV
pF
mV
mV
mA
mA
%
ps
ps
ISOUTNP Output Current
DRIVER AC SPECIFICATIONS
Clock
Clock Signal Duty Cycle
Minimum Data Setup TIme(4, 5)
Minimum Data Hold Time(4, 5)
tRISE/tFALL
VOD Rise Time or VOD Fall Time
The DC specifications refer to the condition where the LVDS outputs are not switching, but are permanently at a valid logic level 0 or 1.
VOS refers to the common-mode of OUTP and OUTN.
Output capacitance inside the device, from either OUTP or OUTN to ground.
Refer to the LVDS application note (SBAA118) for a description of data setup and hold times.
Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume that the data and clock
paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as reduced timing margins.
4
ADS5272
www.ti.com
SBAS324 − JUNE 2004
SWITCHING CHARACTERISTICS
TMIN = −40°C, TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V,
LVDD = 3.3V, −1dBFS, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted.
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