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49FCT805APYI8

Description
Clock Driver, CMOS, PDSO20
Categorylogic    logic   
File Size68KB,7 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

49FCT805APYI8 Overview

Clock Driver, CMOS, PDSO20

49FCT805APYI8 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Reach Compliance Codenot_compliant
JESD-30 codeR-PDSO-G20
JESD-609 codee0
MaximumI(ol)0.064 A
Humidity sensitivity level1
Number of terminals20
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSSOP
Encapsulate equivalent codeSSOP20,.3
Package shapeRECTANGULAR
Package formSMALL OUTLINE, SHRINK PITCH
power supply5 V
Prop。Delay @ Nom-Sup5.3 ns
Certification statusNot Qualified
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formGULL WING
Terminal pitch0.635 mm
Terminal locationDUAL
Base Number Matches1
IDT49FCT805/A
FAST CMOS BUFFER/CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
FAST CMOS
BUFFER/CLOCK DRIVER
IDT49FCT805/A
FEATURES:
0.5 MICRON CMOS Technology
Guaranteed low skew < 700ps (max.)
Low duty cycle distortion < 1ns (max.)
Low CMOS power levels
TTL compatible inputs and outputs
Rail-to-rail output voltage swing
High drive: -24mA I
OH
, +64mA I
OL
Two independent output banks with 3-state control
1:5 fanout per bank
"Heartbeat" monitor output
Available in SSOP and SOIC packages
DESCRIPTION:
The 49FCT805 is a non-inverting buffer/clock driver built using ad-
vanced dual metal CMOS technology. Each bank consists of two banks of
drivers. Each bank drives five output buffers from a standard TTL
compatible input. These devices feature a “heart-beat” monitor for
diagnostics and PLL driving. The MON output is identical to all other outputs
and complies with the output specifications in this document.
The 49FCT805 offers low capacitance inputs and hysteresis. Rail-to-rail
output swing improves noise margin and allows easy interface with CMOS
inputs.
NOTE: EOL for non-green parts to occur on 5/13/10 per
PDN U-09-01
FUNCTIONAL BLOCK DIAGRAM
OE
A
IN
A
5
OA
1
-OA
5
IN
B
5
OB
1
-OB
5
OE
B
MON
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
1
c
2006
Integrated Device Technology, Inc.
SEPT. 2009
DSC-5836/5

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