UL634H256
Low Voltage
PowerStore
32K x 8 nvSRAM
Features
High-performance CMOS non-
volatile static RAM 32768 x 8 bits
35 and 45 ns Access Times
15 and 20 ns Output Enable
Access Times
I
CC
= 8 mA typ. at 200 ns Cycle
Time
Automatic STORE to EEPROM
on Power Down using external
capacitor
Software initiated STORE
Automatic STORE Timing
10
6
STORE cycles to EEPROM
100 years data retention in
EEPROM
Automatic RECALL on Power Up
Software RECALL Initiation
Unlimited RECALL cycles from
EEPROM
Wide voltage range: 2.7 ... 3.6 V
(3.0 ... 3.6 V for 35 ns type)
Operating temperature range:
0 to 70 °C
-40 to 85 °C
QS 9000 Quality Standard
ESD protection > 2000 V
(MIL STD 883C M3015.7-HBM)
RoHS compliance and Pb- free
Package: SOP 32 (300 mil)
Description
The UL634H256 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disab-
led.
The UL634H256 is a fast static
RAM (35 and 45 ns), with a nonvo-
latile electrically erasable PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM.
Data transfers from the SRAM to
the EEPROM (the STORE opera-
tion) take place automatically upon
power down using charge stored in
an external 68 µF capacitor. Trans-
fers from the EEPROM to the
SRAM (the RECALL operation)
take place automatically on power
up.
The UL634H256 combines the
high performance and ease of use
of a fast SRAM with nonvolatile
data integrity.
STORE cycles also may be initia-
ted under user control via a soft-
ware sequence or via a single pin
(HSB).
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
RECALL cycles may also be initia-
ted by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
Pin Configuration
Pin Description
Signal Name
VCAP
A14
A12
A7
A6
A5
A4
A3
n.c.
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCCX
HSB
W
A13
A8
A9
A11
G
n.c.
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
G
A11
A9
A8
A13
W
HSB
VCCX
VCAP
A14
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
n.c.
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
n.c.
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
Capacitor
Hardware Controlled Store/Busy
A0 - A14
DQ0 - DQ7
E
G
W
VCCX
VSS
VCAP
HSB
SOP
TSOP
Top View
Top View
April 7, 2005
1
UL634H256
Block Diagram
A5
A6
A7
A8
A9
A11
A12
A13
A14
DQ0
DQ1
Input Buffers
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
EEPROM Array
512 x (64 x 8)
STORE
Row Decoder
SRAM
Array
512 Rows x
64 x 8 Columns
Store/
Recall
Control
V
CCX
V
SS
V
CAP
Power
Control
RECALL
V
CCX
V
CAP
HSB
Column I/O
Column Decoder
Software
Detect
A0 - A13
A0 A1 A2 A3 A4 A10
G
E
W
Truth Table for SRAM Operations
Operating Mode
Standby/not selected
Internal Read
Read
Write
*
H or L
Characteristics
All voltages are referenced to V
SS
= 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of
≤
5 ns, measured between 10 % and 90 % of V
I
, as well as
input levels of V
IL
= 0 V and V
IH
= 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the t
dis
-times and t
en
-times, in which cases transition is measured
±
200 mV from steady-state voltage.
E
H
L
L
L
HSB
H
H
H
H
W
*
G
*
DQ0 - DQ7
High-Z
High-Z
Data Outputs Low-Z
Data Inputs High-Z
H
H
L
H
L
*
Absolute Maximum Ratings
a
Power Supply Voltage
Input Voltage
Output Voltage
Power Dissipation
Operating Temperature
C-Type
K-Type
A-Type
Symbol
V
CC
V
I
V
O
P
D
T
a
Min.
-0.5
-0.3
-0.3
Max.
4.6
V
CC
+0.5
V
CC
+0.5
1
Unit
V
V
V
W
°C
°C
°C
°C
0
-40
-40
-65
70
85
125
150
Storage Temperature
a:
T
stg
Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2
April 7, 2005
UL634H256
Recommended
Operating Conditions
Power Supply Voltage
b
Symbol
V
CC
Conditions
t
c
= 35 ns
t
c
= 45 ns
-2 V at Pulse Width
10 ns permitted
Min.
3.0
2.7
-0.3
2.2
Max.
3.6
3.6
0.8
V
CC
+0.3
Unit
V
V
V
V
Input Low Voltage
Input High Voltage
V
IL
V
IH
C-Type
DC Characteristics
Operating Supply Current
c
Symbol
I
CC1
V
CC
V
IL
V
IH
t
c
t
c
Average Supply Current during
STORE
c
I
CC2
V
CC
E
W
V
IL
V
IH
V
CC
V
IL
V
IH
V
CC
E
t
c
t
c
Operating Supply Current
at t
cR
= 200 ns
c
(Cycling CMOS Input Levels)
Standby Supply Curent
d
(Stable CMOS Input Levels)
I
CC3
V
CC
W
V
IL
V
IH
V
CC
E
V
IL
V
IH
Conditions
Min.
= 3.6 V
= 0.8 V
= 2.2 V
= 35 ns
= 45 ns
= 3.6 V
≤
0.2 V
≥
V
CC
-0.2 V
≤
0.2 V
≥
V
CC
-0.2 V
= 2.7 V
= 0.2 V
≥
V
CC
-0.2 V
= 3.6 V
= V
IH
= 35 ns
= 45 ns
= 3.6 V
≥
V
CC
-0.2 V
≤
0.2 V
≥
V
CC
-0.2 V
= 3.6 V
≥
V
CC
-0.2 V
≤
0.2 V
≥
V
CC
-0.2 V
11
9
10
45
35
3
Max.
K-Type
Min.
Max.
A-Type
Unit
Min.
Max.
47
37
4
-
40
4
mA
mA
mA
Average Supply Current during
PowerStore
Cycle
Standby Supply Current
d
(Cycling TTL Input Levels)
I
CC4
2
2
3
mA
I
CC(SB)1
12
10
11
-
12
12
mA
mA
mA
I
CC(SB)
1
1
1
mA
b: V
CC
reference levels throughout this datasheet refer to V
CCX
if that is where the power supply connection is made, or V
CAP
if V
CCX
is con-
nected to ground.
c: I
CC1
and I
CC3
are depedent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
The current I
CC1
is measured for WRITE/READ - ratio of 1/2.
I
CC2
is the average current required for the duration of the STORE cycle (STORE Cycle Time).
d: Bringing E
≥
V
IH
will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION
table. The current I
CC(SB)1
is measured for WRITE/READ - ratio of 1/2.
April 7, 2005
3
UL634H256
DC Characteristics
Symbol
V
CC
I
OH
I
OL
V
CC
V
OH
V
OL
V
CC
High
Low
Output Leakage Current
High at Three-State- Output
Low at Three-State- Output
I
OHZ
I
OLZ
I
IH
I
IL
V
IH
V
IL
V
CC
V
OH
V
OL
Conditions
= V
CC
min
=-2 mA
= 2 mA
= V
CC
min
= 2.4 V
= 0.4 V
= 3.6 V
= 3.6 V
= 0V
= 3.6 V
= 3.6 V
= 0V
1
-1
µA
µA
1
-1
µA
µA
Min.
Max.
Unit
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Input Leakage Current
V
OH
V
OL
I
OH
I
OL
2.4
0.4
-2
2
V
V
mA
mA
SRAM Memory Operations
Switching Characteristics
No.
Read Cycle
1
2
3
4
5
6
7
8
9
Read Cycle Time
f
Address Access Time to Data Valid
g
Chip Enable Access Time to Data Valid
Output Enable Access Time to Data
Valid
E HIGH to Output in High-Z
h
G HIGH to Output in High-Z
h
E LOW to Output in Low-Z
G LOW to Output in Low-Z
Output Hold Time after Address Change
Symbol
Alt.
t
AVAV
t
AVQV
t
ELQV
t
GLQV
t
EHQZ
t
GHQZ
t
ELQX
t
GLQX
t
AXQX
t
ELICCH
t
EHICCL
IEC
t
cR
t
a(A)
t
a(E)
t
a(G)
t
dis(E)
t
dis(G)
t
en(E)
t
en(G)
t
v(A)
t
PU
t
PD
5
0
3
0
Min.
35
35
Max.
Min.
45
35
35
15
13
13
5
0
3
0
35
45
Unit
Max.
ns
45
45
20
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
45
ns
10 Chip Enable to Power Active
e
11 Chip Disable to Power Standby
d, e
e:
f:
g:
h:
Parameter guaranteed but not tested.
Device is continuously selected with E and G both LOW.
Address valid prior to or coincident with E transition LOW.
Measured
±
200 mV from steady state output voltage.
4
April 7, 2005
UL634H256
Read Cycle 1: Ai-controlled (during Read cycle: E = G = V
IL
, W = V
IH
)
f
t
cR
(1)
Ai
DQi
Output
Previous Data Valid
t
v(A)
(9)
Address Valid
t
a(A)
(2)
Output Data Valid
Read Cycle 2: G-, E-controlled (during Read cycle: W = V
IH
)
g
t
cR
(1)
Ai
E
G
DQi
Output
High Impedance
t
PU
(10)
ACTIVE
STANDBY
Address Valid
t
a(A)
(2)
t
a(E)
(3)
t
en(E)
(7)
t
en(G)
(8)
Output Data Valid
t
a(G)
(4)
t
PD
(11)
t
dis(E)
(5)
t
dis(G)
(6)
I
CC
Switching Characteristics
No.
Write Cycle
12 Write Cycle Time
13 Write Pulse Width
14 Write Pulse Width Setup Time
15 Address Setup Time
16 Address Valid to End of Write
17 Chip Enable Setup Time
18 Chip Enable to End of Write
19 Data Setup Time to End of Write
20 Data Hold Time after End of Write
21 Address Hold after End of Write
22 W LOW to Output in High-Z
h, i
23 W HIGH to Output in Low-Z
Symbol
Alt. #1 Alt. #2
t
AVAV
t
WLWH
t
WLEH
t
AVWL
t
AVWH
t
ELWH
t
ELEH
t
DVWH
t
WHDX
t
WHAX
t
WLQZ
t
WHQX
t
DVEH
t
EHDX
t
EHAX
t
AVEL
t
AVEH
t
AVAV
IEC
t
cW
t
w(W)
t
su(W)
t
su(A)
t
su(A-WH)
t
su(E)
t
w(E)
t
su(D)
t
h(D)
t
h(A)
t
dis(W)
t
en(W)
5
Min.
35
Max.
45
Unit
Min.
45
30
30
0
30
30
30
15
0
0
13
5
15
Max.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
35
25
25
0
25
25
25
12
0
0
April 7, 2005
5
Analogue and Mixed Signal
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