5962R9581901VQC datasheet, PDF

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5962R9581901VQC: Description24 I/O, PIA-GENERAL PURPOSE, CDIP40, SIDE BRAZED, CERAMIC, DIP-40; CategoryThe embedded processor and controller Microcontrollers and processors; File Size240KB，22 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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5962R9581901VQC Overview

24 I/O, PIA-GENERAL PURPOSE, CDIP40, SIDE BRAZED, CERAMIC, DIP-40

5962R9581901VQC Parametric

Parameter Name	Attribute value
Parts packaging code	DIP
package instruction	DIP, DIP40,.6
Contacts	40
Reach Compliance Code	compliant
ECCN code	EAR99
JESD-30 code	R-CDIP-T40
JESD-609 code	e4
Number of I/O lines	24
Number of ports	3
Number of terminals	40
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP
Encapsulate equivalent code	DIP40,.6
Package shape	RECTANGULAR
Package form	IN-LINE
power supply	5 V
Certification status	Not Qualified
Filter level	MIL-PRF-38535 Class V
Maximum seat height	5.72 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	GOLD
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
total dose	100k Rad(Si) V
width	15.24 mm
uPs/uCs/peripheral integrated circuit type	PARALLEL IO PORT, GENERAL PURPOSE
Base Number Matches	1

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REVISIONS

LTR

DESCRIPTION

Changes to conditions in Table I, addition of Test condition 2 in Figure

4. Editorial changes throughout.

DATE

(YR-MO-DA)

96-11-13

APPROVED

Thomas M. Hess

REV

SHEET

REV

SHEET

REV STATUS

OF SHEETS

REV

SHEET

PREPARED BY

Thomas M. Hess

PMIC N/A

DEFENSE ELECTRONICS SUPPLY CENTER

DAYTON, OHIO 45444

STANDARD

MICROCIRCUIT

DRAWING

THIS DRAWING IS AVAILABLE

FOR USE BY ALL

DEPARTMENTS

AND AGENCIES OF THE

DEPARTMENT OF DEFENSE

CHECKED BY

Thomas M. Hess

APPROVED BY

Monica L. Poelking

MICROCIRCUIT, DIGITAL, RADIATION HARDENED,

CMOS, PROGRAMMABLE PERIPHERAL INTERFACE,

MONOLITHIC SILICON

DRAWING APPROVAL DATE

95-12-28

SIZE

REVISION LEVEL

CAGE CODE

AMSC N/A

SHEET

67268

5962-95819

DESC FORM 193

JUL 94

DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.

5962-E033-97

2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing

shall take precedence.

3. REQUIREMENTS

3.1 Item requirements. The individual item requirements for device class M shall be in accordance with 1.2.1 of MIL-STD-883,

"Provisions for the use of MIL-STD-883 in conjunction with compliant non-JAN devices" and as specified herein. The individual item

requirements for device classes Q and V shall be in accordance with MIL-I-38535 and as specified herein or as modified in the device

manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not effect the form, fit, or function as described

herein.

3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-STD-

883 (see 3.1 herein) for device class M and MIL-I-38535 for device classes Q and V and herein.

3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein.

3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.

3.2.3 Block diagram. The block diagram shall be as specified on figure 2.

3.2.4 Radiation exposure circuit. The radiation exposure circuit shall be as specified on figure 3.

3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical

performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full ambient operating

temperature range.

3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for

each subgroup are defined in table I.

3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. Marking for device class M shall be in accordance with

MIL-STD-883 (see 3.1 herein). In addition, the manufacturer's PIN may also be marked as listed in MIL-BUL-103. Marking for device

classes Q and V shall be in accordance with MIL-I-38535.

3.5.1 Certification/compliance mark. The compliance mark for device class M shall be a "C" as required in MIL-STD-883 (see 3.1 herein).

The certification mark for device classes Q and V shall be a "QML" or "Q" as required in MIL-I-38535.

3.6 Certificate of compliance. For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as

an approved source of supply in MIL-BUL-103 (see 6.7.2 herein). For device classes Q and V, a certificate of compliance shall be required

from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.7.1 herein). The certificate of

compliance submitted to DESC-EC prior to listing as an approved source of supply for this drawing shall affirm that the manufacturer's

product meets, for device class M, the requirements of MIL-STD-883 (see 3.1 herein), or for device classes Q and V, the requirements of

MIL-I-38535 and the requirements herein.

3.7 Certificate of conformance. A certificate of conformance as required for device class M in MIL-STD-883 (see 3.1 herein) or for device

classes Q and V in MIL-I-38535 shall be provided with each lot of microcircuits delivered to this drawing.

3.8 Notification of change for device class M. For device class M, notification to DESC-EC of change of product (see 6.2 herein) involving

devices acquired to this drawing is required for any change as defined in MIL-STD-973.

3.9 Verification and review for device class M. For device class M, DESC, DESC's agent, and the acquiring activity retain the option to

review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available onshore at the

option of the reviewer.

3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group

number 105 (see MIL-I-38535, appendix A).

SIZE

STANDARD

MICROCIRCUIT DRAWING

DEFENSE ELECTRONICS SUPPLY CENTER

DAYTON, OHIO 45444

DESC FORM 193A

JUL 94

REVISION LEVEL

5962-95819

SHEET

5962R9581901VQC Related Products

	5962R9581901VQC	5962R9581901QQC
Description	24 I/O, PIA-GENERAL PURPOSE, CDIP40, SIDE BRAZED, CERAMIC, DIP-40	24 I/O, PIA-GENERAL PURPOSE, CDIP40, SIDE BRAZED, CERAMIC, DIP-40
Parts packaging code	DIP	DIP
package instruction	DIP, DIP40,.6	DIP, DIP40,.6
Contacts	40	40
Reach Compliance Code	compliant	compliant
ECCN code	EAR99	EAR99
JESD-30 code	R-CDIP-T40	R-CDIP-T40
JESD-609 code	e4	e4
Number of I/O lines	24	24
Number of ports	3	3
Number of terminals	40	40
Maximum operating temperature	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP	DIP
Encapsulate equivalent code	DIP40,.6	DIP40,.6
Package shape	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	IN-LINE
power supply	5 V	5 V
Certification status	Not Qualified	Not Qualified
Filter level	MIL-PRF-38535 Class V	MIL-PRF-38535 Class Q
Maximum seat height	5.72 mm	5.72 mm
Maximum supply voltage	5.5 V	5.5 V
Minimum supply voltage	4.5 V	4.5 V
Nominal supply voltage	5 V	5 V
surface mount	NO	NO
technology	CMOS	CMOS
Temperature level	MILITARY	MILITARY
Terminal surface	GOLD	GOLD
Terminal form	THROUGH-HOLE	THROUGH-HOLE
Terminal pitch	2.54 mm	2.54 mm
Terminal location	DUAL	DUAL
total dose	100k Rad(Si) V	100k Rad(Si) V
width	15.24 mm	15.24 mm
uPs/uCs/peripheral integrated circuit type	PARALLEL IO PORT, GENERAL PURPOSE	PARALLEL IO PORT, GENERAL PURPOSE
Base Number Matches	1	1

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