DATASHEET
FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER
ICS342
Description
The ICS342 is a low cost, dual-output, field programmable
clock synthesizer. The ICS342 can generate two output
frequencies from 250 kHz to 200 MHz, using up to two
independently configurable PLLs. The outputs may employ
Spread Spectrum techniques to reduce system
electro-magnetic interference (EMI).
Using ICS’ VersaClock
TM
software to configure the PLL and
output, the ICS342 contains a One-Time Programmable
(OTP) ROM to allow field programmability. Programming
features include 2 selectable configuration registers. Using
Phase-Locked Loop (PLL) techniques, the device runs from
a standard fundamental mode, inexpensive crystal, or
clock. It can replace multiple crystals and oscillators, saving
board space and cost.
The device also has a power down feature that tri-states the
clock outputs and turns off the PLLs when the PDTS pin is
taken low.
The ICS342 is also available in factory programmed custom
versions for high-volume applications.
Features
•
8-pin SOIC package
•
Highly accurate frequency generation
•
M/N Multiplier PLL: M = 1...2048, N = 1...1024
•
Output clock frequencies up to 200 MHz
•
Two ROM locations for frequency and spread selection
•
Spread spectrum capability for lower system EMI
•
Center or Down Spread up to 4% total
•
Selectable 32 kHz or 120 kHz modulation
•
Input crystal frequency from 5 to 27 MHz
•
Input clock frequency from 2 to 50 MHz
•
Operating voltage of 3.3 V
•
Advanced, low power CMOS process
•
For one output clock, use the ICS341. For three output
•
clocks, see the ICS343. For more than three outputs, see
the ICS345 or ICS348.
Available in Pb (lead) free packaging
Block Diagram
VDD
SEL
Crystal or
clock input
X1/ICLK
OTP ROM
with PLL
Divider
Values
CLK1
PLL Clock Synthesis,
Spred Spectrum and
Control Circuitry
Crystal
Oscillator
X2
External capacitors are
required with a crystal input.
CLK2
GND
PDTS (both outputs and PLL)
IDT™ / ICS™
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Pin Assignment
X1/ I CLK
VDD
GND
CLK1
1
2
3
4
8
7
6
5
X2
PDTS
SEL
CLK2
Output Clock Selection Table
SEL CLK1 (MHz) CLK2 (MHz)
0
1
User
Configurable
User
Configurable
User
Configurable
User
Configurable
Spread
Percentage
User
Configurable
User
Configurable
8-pin (150 mil) SOIC
Pin Description
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
X1/ICLK
VDD
GND
CLK1
CLK2
SEL
PDTS
X2
Pin
Type
XI
Power
Power
Output
Output
Input
Input
XO
Connect to +3.3 V.
Connect to ground.
Pin Description
Connect this pin to a crystal or external clock input.
Clock output. Weak internal pull-down when tri-state.
Clock output. Weak internal pull-down when tri-state.
Select for frequency selection on CLK1 and CLK2. Internal pull-up resistor.
Powers down entire chip. Tri-states CLK outputs when low. Internal pull-up
resistor.
Connect this pin to a crystal, or float for clock input.
External Components
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a commonly
used trace impedance), place a 33Ω resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20Ω.
the board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no vias) been the crystal and device. Crystal
capacitors must be connected from each of the pins X1 and
X2 to ground.
The value (in pF) of these crystal caps should equal (C
L
-6
pF)*2. In this equation, C
L
= crystal load capacitance in pF.
Example: For a crystal with a 16 pF load capacitance, each
crystal capacitor would be 20 pF [(16-6) x 2] = 20.
Decoupling Capacitor
As with any high-performance mixed-signal IC, the ICS342
must be isolated from system power supply noise to perform
optimally.
A decoupling capacitor of 0.01µF must be connected
between VDD and the PCB ground plane.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to ground.
These capacitors are used to adjust the stray capacitance of
IDT™ / ICS™
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possible. No vias should be used between the decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
2) The external crystal should be mounted just next to the
device with short traces. The X1 and X2 traces should not
be routed next to each other with minimum spaces, instead
they should be separated and away from other traces.
3) To minimize EMI, the 33Ω series termination resistor (if
needed) should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers. Other signal traces should be routed away from the
ICS342. This includes signal traces just underneath the
device, or on layers adjacent to the ground plane layer used
by the device.
output frequencies.
VersaClock software quickly evaluates accessible VCO
frequencies with available output divide values and provides
an easy to understand, bar code rating for the target output
frequencies. The user may evaluate output accuracy,
performance trade-off scenarios in seconds.
Spread Spectrum Modulation
The ICS342 utilizes frequency modulation (FM) to distribute
energy over a range of frequencies. By modulating the
output clock frequencies, the device effectively lowers
energy across a broader range of frequencies; thus,
lowering a system’s electromagnetic interference (EMI). The
modulation rate is the time from transitioning from a
minimum frequency to a maximum frequency and then back
to the minimum.
Spread Spectrum Modulation can be applied as either
“center spread” or “down spread”. During center spread
modulation, the deviation from the target frequency is equal
in the positive and negative directions. The effective
average frequency is equal to the target frequency. In
applications where the clock is driving a component with a
maximum frequency rating, down spread should be applied.
In this case, the maximum frequency, including modulation,
is the target frequency. The effective average frequency is
less than the target frequency.
The ICS342 operates in both center spread and down
spread modes. For center spread, the frequency can be
modulated between +/- 0.125% to +/-2.0%. For down
spread, the frequency can be modulated between -0.25% to
-4.0%.
Both output frequency banks will utilize identical spread
spectrum percentage deviations and modulation rates, if a
common VCO frequency can be identified.
ICS342 Configuration Capabilities
The architecture of the ICS342 allows the user to easily
configure the device to a wide range of output frequencies,
for a given input reference frequency.
The frequency multiplier PLL provides a high degree of
precision. The M/N values (the multiplier/divide values
available to generate the target VCO frequency) can be set
within the range of M = 1 to 2048 and N = 1 to 1024.
The ICS342 also provides separate output divide values,
from 2 through 20, to allow the two output clock banks to
support widely differing frequency values from the same
PLL.
Each output frequency can be represented as:
OutputFreq
=
REFFreq
-------------------------------------
-
OutputDivide
----
-
⋅
M
N
Spread Spectrum Modulation Rate
The spread spectrum modulation frequency applied to the
output clock frequency may occur at a variety of rates. For
applications requiring the driving of “down-circuit” PLLs,
Zero Delay Buffers, or those adhering to PCI standards, the
spread spectrum modulation rate should be set to 30-33
kHz. For other applications, a 120 kHz modulation option is
available.
ICS VersaClock Software
ICS applies years of PLL optimization experience into a user
friendly software that accepts the user’s target reference
clock and output frequencies and generates the lowest jitter,
lowest power configuration, with only a press of a button.
The user does not need to have prior PLL experience or
determine the optimal VCO frequency to support multiple
IDT™ / ICS™
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Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS342. These ratings, which are
standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at
these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Parameter
Supply Voltage, VDD
Inputs
Clock Outputs
Storage Temperature
Soldering Temperature
Junction Temperature
Condition
Referenced to GND
Referenced to GND
Referenced to GND
Max 10 seconds
Min.
-0.5
-0.5
-65
Typ.
Max.
7
VDD+ 0.5
VDD+ 0.5
150
260
125
Units
V
V
V
°C
°C
°C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature (ICS342M)
Ambient Operating Temperature (ICS342MI)
Power Supply Voltage (measured in respect to GND)
Power Supply Ramp Time
Min.
0
-40
+3.15
Typ.
Max.
+70
+85
Units
°C
°C
V
ms
+3.3
+3.45
4
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DC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3V ±5%,
Ambient Temperature -40 to +85°C
Parameter
Operating Voltage
Symbol
VDD
Conditions
Configuration
Dependent - See
VersaClock
TM
Estimates
Min.
3.15
Typ.
3.3
Max.
3.45
Units
V
mA
Operating Supply Current
Input High Voltage
IDD
Two 33.3333 MHz
outputs, PDTS = 1, no
load, Note 1
PDTS = 0
SEL pin
SEL pin
VDD-0.5
2
13
mA
20
0.4
0.4
Input High Voltage
Input Low Voltage
Input High Voltage, PDTS
Input Low Voltage, PDTS
Input High Voltage
Input Low Voltage
Output High Voltage
(CMOS High)
Output High Voltage
Output Low Voltage
Short Circuit Current
Nominal Output
Impedance
Internal pull-up resistor
Internal pull-down
resistor
Input Capacitance
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OH
V
OL
I
OS
Z
O
R
PUP
R
PD
C
IN
µA
V
V
V
V
V
VDD/2-1
V
V
V
0.4
V
mA
Ω
kΩ
kΩ
pF
ICLK
ICLK
I
OH
= -4 mA
I
OH
= -12 mA
I
OL
= 12mA
VDD/2+1
VDD-0.4
2.4
±70
20
SEL, PDTS pins
CLK output
Inputs
250
525
4
Note 1: Example with 25 MHz crystal input with two outputs of 33.3 MHz, no load, and VDD = 3.3 V.
IDT™ / ICS™
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ICS342
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