W83877TD datasheet, PDF - EEWORLD Datasheet

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W83877TD: DescriptionMicrocontroller, CMOS, PQFP100; CategoryThe embedded processor and controller Microcontrollers and processors; File Size946KB，154 Pages; ManufacturerNuvoton Technology Corporation; Websitehttp://www.nuvoton.com.cn/hq/

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W83877TD Overview

Microcontroller, CMOS, PQFP100

W83877TD Parametric

Parameter Name	Attribute value
Maker	Nuvoton Technology Corporation
Parts packaging code	QFP
package instruction	QFP, QFP100,.63X.87
Contacts	100
Reach Compliance Code	compliant
JESD-30 code	R-PQFP-G100
Number of terminals	100
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP100,.63X.87
Package shape	RECTANGULAR
Package form	FLATPACK
power supply	5 V
Certification status	Not Qualified
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.635 mm
Terminal location	QUAD
uPs/uCs/peripheral integrated circuit type	MULTIFUNCTION PERIPHERAL
Base Number Matches	1

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WINBOND I/O

W83877TF/W83877TG

Release Date: May 2006 Version: 0.7

W83877TF/W83877TG

Table of Contents-

GENERAL DESCRIPTION .............................................................................................................. 1

FEATURES ...................................................................................................................................... 2

PIN CONFIGURATION .................................................................................................................... 4

PIN DESCRIPTION......................................................................................................................... 5

4.1

4.2

4.3

4.4

5.1

Host Interface.......................................................................................................................... 5

Serial Port Interface ................................................................................................................ 7

Multi-Mode Parallel Port.......................................................................................................... 8

FDC Interface........................................................................................................................ 13

W83877TF/TG FDC .............................................................................................................. 15

5.1.1

5.1.2

5.1.3

5.1.4

5.1.5

5.1.6

5.1.7

5.1.8

5.1.9

AT interface ............................................................................................................................15

FIFO (Data) ............................................................................................................................15

Data Separator .......................................................................................................................16

Write Precompensation ..........................................................................................................16

Perpendicular Recording Mode ..............................................................................................16

Tape Drive..............................................................................................................................17

FDC Core ...............................................................................................................................17

FDC Commands.....................................................................................................................17

FDC Instruction Sets ..............................................................................................................18

Status Register A (SA Register) (Read base address + 0).....................................................26

Status Register B (SB Register) (Read base address + 1).....................................................28

Digital Output Register (DO Register) (Write base address + 2) ............................................30

Tape Drive Register (TD Register) (Read base address + 3).................................................30

Main Status Register (MS Register) (Read base address + 4)...............................................31

Data Rate Register (DR Register) (Write base address + 4) ..................................................31

FIFO Register (R/W base address + 5) ..................................................................................33

Digital Input Register (DI Register) (Read base address + 7).................................................34

Configuration Control Register (CC Register) (Write base address + 7) ................................36

FDC FUNCTIONAL DESCRIPTION .............................................................................................. 15

5.2

Register Descriptions ............................................................................................................ 26

5.2.1

5.2.2

5.2.3

5.2.4

5.2.5

5.2.6

5.2.7

5.2.8

5.2.9

UART PORT................................................................................................................................... 37

6.1

6.2

Universal Asynchronous Receiver/Transmitter (UART A, UART B) .................................... 37

Register Address................................................................................................................... 37

6.2.1

6.2.2

6.2.3

6.2.4

UART Control Register (UCR) (Read/Write) ..........................................................................38

UART Status Register (USR) (Read/Write) ............................................................................39

Handshake Control Register (HCR) (Read/Write) ..................................................................40

Handshake Status Register (HSR) (Read/Write)....................................................................41

-II -

W83877TF/W83877TG

6.2.5

6.2.6

6.2.7

6.2.8

6.2.9

UART FIFO Control Register (UFR) (Write only)....................................................................42

Interrupt Status Register (ISR) (Read only) ............................................................................43

Interrupt Control Register (ICR) (Read/Write).........................................................................44

Programmable Baud Generator (BLL/BHL) (Read/Write).......................................................44

User-defined Register (UDR) (Read/Write) ............................................................................45

PARALLEL PORT ......................................................................................................................... 46

7.1

7.2

Printer Interface Logic ........................................................................................................... 46

Enhanced Parallel Port (EPP)............................................................................................... 48

7.2.1

7.2.2

7.2.3

7.2.4

7.2.5

7.2.6

7.2.7

7.2.8

Data Swapper.........................................................................................................................48

Printer Status Buffer ...............................................................................................................48

Printer Control Latch and Printer Control Swapper.................................................................49

EPP Address Port...................................................................................................................49

EPP Data Port 0-3 ..................................................................................................................50

Bit Map of Parallel Port and EPP Registers............................................................................50

EPP Pin Descriptions .............................................................................................................51

EPP Operation .......................................................................................................................51

ECP Register and Mode Definitions .......................................................................................52

Data and ecpAFifo Port ..........................................................................................................53

Device Status Register (DSR) ................................................................................................53

Device Control Register (DCR)...............................................................................................54

cFifo (Parallel Port Data FIFO) Mode = 010 ...........................................................................54

ecpDFifo (ECP Data FIFO) Mode = 011.................................................................................54

tFifo (Test FIFO Mode) Mode = 110 .......................................................................................55

cnfgA (Configuration Register A) Mode = 111 ........................................................................55

cnfgB (Configuration Register B) Mode = 111 ........................................................................55

ecr (Extended Control Register) Mode = all............................................................................56

Bit Map of ECP Port Registers ...............................................................................................57

ECP Pin Descriptions .............................................................................................................58

ECP Operation .......................................................................................................................59

FIFO Operation ......................................................................................................................59

DMA Transfers .......................................................................................................................60

Programmed I/O (NON-DMA) Mode.......................................................................................60

7.3

Extended Capabilities Parallel (ECP) Port............................................................................ 52

7.3.1

7.3.2

7.3.3

7.3.4

7.3.5

7.3.6

7.3.7

7.3.8

7.3.9

7.3.10

7.3.11

7.3.12

7.3.13

7.3.14

7.3.15

7.3.16

7.4

7.5

Extension FDD Mode (EXTFDD) .......................................................................................... 60

Extension 2FDD Mode (EXT2FDD) ...................................................................................... 60

PLUG AND PLAY CONFIGURATION ........................................................................................... 61

ACPI /LEGACY FEATURE AND AUTO POWER MANAGEMENT ............................................... 61

9.1

9.2

ACPI/Legacy power management ........................................................................................ 61

Device(auto) power management......................................................................................... 61

Publication Release Date: May 2006

Revision 0.7

-III-

W83877TF/W83877TG

10. SERIAL IRQ ................................................................................................................................... 62

10.1 Start Frame ........................................................................................................................... 63

10.2 IRQ/Data Frame.................................................................................................................... 63

10.3 Stop Frame ........................................................................................................................... 64

10.4 Reset and Initialization .......................................................................................................... 64

11. EXTENDED FUNCTION REGISTERS .......................................................................................... 65

11.1 Extended Functions Enable Registers (EFERs)................................................................... 65

11.2 Extended Function Index Registers (EFIRs), Extended Function Data Registers(EFDRs) . 66

11.2.1

11.2.2

11.2.3

11.2.4

11.2.5

11.2.6

11.2.7

11.2.8

11.2.9

Configuration Register 0 (CR0), default = 00H .......................................................................66

Configuration Register 1 (CR1), default = 00H .......................................................................67

Configuration Register 2 (CR2), default = 00H .......................................................................68

Configuration Register 3 (CR3), default = 30H .......................................................................68

Configuration Register 4 (CR4), default = 00H .......................................................................69

Configuration Register 5 (CR5), default = 00H .......................................................................70

Configuration Register 6 (CR6), default = 00H .......................................................................70

Configuration Register 7 (CR7), default = 00H .......................................................................72

Configuration Register 8 (CR8), default = 00H .......................................................................73

11.2.10 Configuration Register 9 (CR9), default = 0CH ......................................................................74

11.2.11 Configuration Register A (CR0A), default = 00H ....................................................................75

11.2.12 Configuration Register B (CR0B), default = 0CH....................................................................75

11.2.13 Configuration Register C (CR0C), default = 28H ....................................................................76

11.2.14 Configuration Register D (CR0D), default = A3H ...................................................................78

11.2.15 Configuration Register E (CR0E), Configuration Register F (CR0F) ......................................79

11.2.16 Configuration Register 10 (CR10), default = 00H ...................................................................80

11.2.17 Configuration Register 11 (CR11), default = 00H ...................................................................80

11.2.18 Configuration Register 12 (CR12), default = 00H ...................................................................81

11.2.19 Configuration Register 13 (CR13), default = 00H ...................................................................81

11.2.20 Configuration Register 14 (CR14), default = 00H ...................................................................82

11.2.21 Configuration Register 15 (CR15), default = 00H ...................................................................83

11.2.22 Configuration Register 16 (CR16), default = 04H ...................................................................85

11.2.23 Configuration Register 17 (CR17), default = 00H ...................................................................86

11.2.24 Configuration Register 18 (CR18), default=00H .....................................................................87

11.2.25 Configuration Register 19 (CR19), default=00H .....................................................................88

11.2.26 Configuration Register 20 (CR20) ..........................................................................................89

11.2.27 Configuration Register 23 (CR23) ..........................................................................................89

11.2.28 Configuration Register 24 (CR24) ..........................................................................................90

11.2.29 Configuration Register 25 (CR25) ..........................................................................................90

11.2.30 Configuration Register 26 (CR26) ..........................................................................................91

11.2.31 Configuration Register 27 (CR27) ..........................................................................................91

11.2.32 Configuration Register 28 (CR28) ..........................................................................................93

-IV -

W83877TD Related Products

	W83877TD	W83877TF
Description	Microcontroller, CMOS, PQFP100	Microcontroller, CMOS, PQFP100
Maker	Nuvoton Technology Corporation	Nuvoton Technology Corporation
Parts packaging code	QFP	QFP
package instruction	QFP, QFP100,.63X.87	QFP, QFP100,.75X.99
Contacts	100	100
Reach Compliance Code	compliant	compliant
JESD-30 code	R-PQFP-G100	R-PQFP-G100
Number of terminals	100	100
Maximum operating temperature	70 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QFP	QFP
Encapsulate equivalent code	QFP100,.63X.87	QFP100,.75X.99
Package shape	RECTANGULAR	RECTANGULAR
Package form	FLATPACK	FLATPACK
power supply	5 V	5 V
Certification status	Not Qualified	Not Qualified
Nominal supply voltage	5 V	5 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL
Terminal form	GULL WING	GULL WING
Terminal pitch	0.635 mm	0.635 mm
Terminal location	QUAD	QUAD
Base Number Matches	1	1

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