74LVC2G125GT datasheet, PDF - EEWORLD Datasheet

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74LVC2G125GT: DescriptionBus Driver, LVC/LCX/Z Series, 2-Func, 1-Bit, True Output, CMOS, PDSO8; Categorylogic logic; File Size285KB，22 Pages; ManufacturerNexperia; Websitehttps://www.nexperia.com; Environmental Compliance

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74LVC2G125GT Overview

Bus Driver, LVC/LCX/Z Series, 2-Func, 1-Bit, True Output, CMOS, PDSO8

74LVC2G125GT Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
package instruction	VSON,
Reach Compliance Code	compliant
series	LVC/LCX/Z
JESD-30 code	R-PDSO-N8
JESD-609 code	e3
length	1.95 mm
Logic integrated circuit type	BUS DRIVER
Humidity sensitivity level	1
Number of digits	1
Number of functions	2
Number of ports	2
Number of terminals	8
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	VSON
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260
propagation delay (tpd)	11.4 ns
Certification status	Not Qualified
Maximum seat height	0.5 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	1.65 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Tin (Sn)
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	1 mm
Base Number Matches	1

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74LVC2G125

Dual bus buffer/line driver; 3-state

Rev. 14 — 29 March 2013

Product data sheet

1. General description

The 74LVC2G125 provides a dual non-inverting buffer/line driver with 3-state output.

The 3-state output is controlled by the output enable input (pin nOE). A HIGH-level at pin

nOE causes the output to assume a high-impedance OFF-state. Schmitt trigger action at

all inputs makes the circuit highly tolerant of slower input rise and fall times.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these

devices as translators in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial power-down applications using I

OFF

. The I

OFF

circuitry disables the output, preventing a damaging backflow current through the device

when it is powered down.

2. Features and benefits



Wide supply voltage range from 1.65 V to 5.5 V

5 V tolerant input/output for interfacing with 5 V logic

High noise immunity

Complies with JEDEC standard:



JESD8-7 (1.65 V to 1.95 V)



JESD8-5 (2.3 V to 2.7 V)



JESD8-B/JESD36 (2.7 V to 3.6 V)

ESD protection:



HBM JESD22-A114F exceeds 2000 V



MM JESD22-A115-A exceeds 200 V

24

mA output drive (V

= 3.0 V)

CMOS low-power consumption

Latch-up performance exceeds 250 mA

Direct interface with TTL levels

Inputs accept voltages up to 5 V

Multiple package options

Specified from

40 C

to +85

C

and

40 C

to +125

C



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