IDT70V05S20JI datasheet, PDF - EEWORLD Datasheet

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IDT70V05S20JI: Description8K X 8 DUAL-PORT SRAM, 20 ns, PQFP64; Categorystorage; File Size174KB，22 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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IDT70V05S20JI Overview

8K X 8 DUAL-PORT SRAM, 20 ns, PQFP64

IDT70V05S20JI Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	64
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	3.6 V
Minimum supply/operating voltage	3 V
Rated supply voltage	3.3 V
maximum access time	20 ns
Processing package description	14 X 14 MM, 1.40 MM HEIGHT, TQFP-64
state	ACTIVE
Craftsmanship	CMOS
packaging shape	SQUARE
Package Size	FLATPACK, LOW PROFILE
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.8000 mm
terminal coating	TIN LEAD
Terminal location	QUAD
Packaging Materials	PLASTIC/EPOXY
Temperature level	INDUSTRIAL
memory width	8
organize	8K X 8
storage density	65536 deg
operating mode	ASYNCHRONOUS
Number of digits	8192 words
Number of digits	8K
Memory IC type	DUAL-PORT SRAM
serial parallel	PARALLEL

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HIGH-SPEED 3.3V

8K x 8 DUAL-PORT

STATIC RAM

Features

IDT70V05S/L

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

– Commercial: 15/20/25/35/55ns (max.)

– Industrial: 20/25/35/55ns (max.)

Low-power operation

– IDT70V05S

Active: 400mW (typ.)

Standby: 3.3mW (typ.)

– IDT70V05L

Active: 380mW (typ.)

Standby: 660

W (typ.)

IDT70V05 easily expands data bus width to 16 bits or more

using the Master/Slave select when cascading more than

one device

M/S = V

for

BUSY

output flag on Master

M/S = V

for

BUSY

input on Slave

Interrupt Flag

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

TTL-compatible, single 3.3V (±0.3V) power supply

Available in 68-pin PGA and PLCC, and a 64-pin TQFP

Industrial temperature range (-40°C to +85°C) is available

for selected speeds

Functional Block Diagram

I/O

- I/O

I/O

Control

I/O

Control

I/O

-I/O

BUSY

(1,2)

12L

Address

Decoder

BUSY

(1,2)

MEMORY

ARRAY

Address

Decoder

12R

SEM

INT

(2)

NOTES:

1. (MASTER):

BUSY

is output; (SLAVE):

BUSY

is input.

BUSY

outputs and

INT

outputs are non-tri-stated push-pull.

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

R/W

SEM

INT

(2)

2941 drw 01

MARCH 2000

DSC 2941/6

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