AT29C040A
Features
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Fast Read Access Time - 120 ns
5-Volt-Only Reprogramming
Sector Program Operation
Single Cycle Reprogram (Erase and Program)
2048 Sectors (256 bytes/sector)
Internal Address and Data Latches for 256-Bytes
Internal Program Control and Timer
Hardware and Software Data Protection
Two 16 KB Boot Blocks with Lockout
Fast Sector Program Cycle Time - 10 ms
DATA Polling for End of Program Detection
Low Power Dissipation
40 mA Active Current
100
µA
CMOS Standby Current
Typical Endurance > 10,000 Cycles
Single 5V
±
10% Supply
CMOS and TTL Compatible Inputs and Outputs
Description
The AT29C040A is a 5-volt-only in-system Flash Programmable and Erasable Read
Only Memory (PEROM). Its 4 megabits of memory is organized as 524,288 words by
8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS EEPROM technology,
the device offers access times up to 120 ns, and a low 220 mW power dissipation.
When the device is deselected, the CMOS standby current is less than 100
µA.
The
device endurance is such that any sector can typically be written to in excess of
10,000 times. The programming algorithm is compatible with other devices in Atmel’s
5-volt-only Flash family.
(continued)
4 Megabit
(512K x 8)
5-volt Only
256-Byte Sector
CMOS Flash
Memory
AT29C040A
Pin Configurations
Pin Name
A0 - A18
CE
OE
WE
Function
Addresses
Chip Enable
Output Enable
Write Enable
I/O0 - I/O7 Data Inputs/Outputs
NC
No Connect
DIP Top View
TSOP Top View
Type 1
0333D
4-165
Description
(Continued)
To allow for simple in-system reprogrammability, the
AT29C040A does not require high input voltages for pro-
gramming. Five-volt-only commands determine the opera-
tion of the device. Reading data out of the device is similar
to reading from an EPROM. Reprogramming the
AT29C040A is performed on a sector basis; 256-bytes of
data are loaded into the device and then simultaneously
programmed.
During a reprogram cycle, the address locations and 256-
bytes of data are internally latched, freeing the address
and data bus for other operations. Following the initiation
of a program cycle, the device will automatically erase the
sector and then program the latched data using an internal
control timer. The end of a program cycle can be detected
by DATA polling of I/O7. Once the end of a program cycle
has been detected, a new access for a read or program
can begin.
Block Diagram
Device Operation
READ:
The AT29C040A is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-
line control gives designers flexibility in preventing bus
contention.
BYTE LOAD:
Byte loads are used to enter the 256-
bytes of a sector to be programmed or the software codes
for data protection. A byte load is performed by applying a
low pulse on the WE or CE input with CE or WE low (re-
spectively) and OE high. The address is latched on the
falling edge of CE or WE, whichever occurs last. The data
is latched by the first rising edge of CE or WE.
PROGRAM:
The device is reprogrammed on a sector
basis. If a byte of data within a sector is to be changed,
data for the entire sector must be loaded into the device.
Any byte that is not loaded during the programming of its
sector will be erased to read FFH. Once the bytes of a
sector are loaded into the device, they are simultaneously
programmed during the internal programming period. Af-
ter the first data byte has been loaded into the device, suc-
cessive bytes are entered in the same manner. Each new
byte to be programmed must have its high to low transition
on WE (or CE) within 150
µs
of the low to high transition of
WE (or CE) of the preceding byte. If a high to low transition
is not detected within 150
µs
of the last low to high transi-
tion, the load period will end and the internal programming
period will start. A8 to A18 specify the sector address. The
sector address must be valid during each high to low tran-
4-166
sition of WE (or CE). A0 to A7 specify the byte address
within the sector. The bytes may be loaded in any order;
sequential loading is not required. Once a programming
operation has been initiated, and for the duration of t
WC
, a
read operation will effectively be a polling operation.
SOFTWARE DATA PROTECTION:
A software control-
led data protection feature is available on the AT29C040A.
Once the software protection is enabled a software algo-
rithm must be issued to the device before a program may
be performed. The software protection feature may be en-
abled or disabled by the user; when shipped from Atmel,
the software data protection feature is disabled. To enable
the software data protection, a series of three program
commands to specific addresses with specific data must
be performed. After the software data protection is en-
abled the same three program commands must begin
each program cycle in order for the programs to occur. All
software program commands must obey the sector pro-
gram timing specifications. The SDP feature protects all
sectors, not just a single sector. Once set, the software
data protection feature remains active unless its disable
command is issued. Power transitions will not reset the
software data protection feature, however the software
feature will guard against inadvertent program cycles dur-
ing power transitions.
After setting SDP, any attempt to write to the device with-
out the three-byte command sequence will start the inter-
nal write timers. No data will be written to the device; how-
ever, for the duration of t
WC
, a read operation will effec-
tively be a polling operation.
(continued)
AT29C040A
AT29C040A
Device Operation
(Continued)
After the software data protection’s 3-byte command code
is given, a byte load is performed by applying a low pulse
on the WE or CE input with CE or WE low (respectively)
and OE high. The address is latched on the falling edge of
CE or WE, whichever occurs last. The data is latched by
the first rising edge of CE or WE. The 256-bytes of data
must be loaded into each sector by the same procedure as
outlined in the program section under device operation.
HARDWARE DATA PROTECTION:
Hardware features
protect against inadvertent programs to the AT29C040A
in the following ways: (a) V
CC
sense— if V
CC
is below 3.8V
(typical), the program function is inhibited. (b) V
CC
power
on delay— once V
CC
has reached the V
CC
sense level,
the device will automatically time out 5 ms (typical) before
programming. (c) Program inhibit— holding any one of OE
low, CE high or WE high inhibits program cycles. (d) Noise
filter— pulses of less than 15 ns (typical) on the WE or CE
inputs will not initiate a program cycle.
PRODUCT IDENTIFICATION:
The product identifica-
tion mode identifies the device and manufacturer as At-
mel. It may be accessed by hardware or software opera-
tion. The hardware operation mode can be used by an ex-
ternal programmer to identify the correct programming al-
gorithm for the Atmel product. In addition, users may wish
to use the software product identification mode to identify
the part (i.e. using the device code), and have the system
software use the appropriate sector size for program op-
erations. In this manner, the user can have a common
board design for 256K to 4-megabit densities and, with
each density’s sector size in a memory map, have the sys-
tem software apply the appropriate sector size.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING:
The AT29C040A features DATA poll-
ing to indicate the end of a program cycle. During a pro-
gram cycle an attempted read of the last byte loaded will
result in the complement of the loaded data on I/O7. Once
the program cycle has been completed, true data is valid
on all outputs and the next cycle may begin. DATA polling
may begin at any time during the program cycle.
TOGGLE BIT:
I n a d d i t i o n t o DATA p o l l i n g t h e
AT29C040A provides another method for determining the
end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from
the device will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will
stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.
OPTIONAL CHIP ERASE MODE:
The entire device
can be erased by using a 6-byte software code. Please
see Software Chip Erase application note for details.
BOOT BLOCK PROGRAMMING LOCKOUT:
The
AT29C040A has two designated memory blocks that have
a programming lockout feature. This feature prevents pro-
gramming of data in the designated block once the feature
has been enabled. Each of these blocks consists of 16K
bytes; the programming lockout feature can be set inde-
pendently for either block. While the lockout feature does
not have to be activated, it can be activated for either or
both blocks.
These two 16K memory sections are referred to as
boot
blocks.
Secure code which will bring up a system can be
contained in a boot block. The AT29C040A blocks are lo-
cated in the first 16K bytes of memory and the last 16K
bytes of memory. The boot block programming lockout
feature can therefore support systems that boot from the
lower addresses of memory or the higher addresses.
Once the programming lockout feature has been acti-
vated, the data in that block can no longer be erased or
programmed; data in other memory locations can still be
changed through the regular programming methods. To
activate the lockout feature, a series of seven program
commands to specific addresses with specific data must
be performed. Please see Boot Block Lockout Feature En-
able Algorithm.
If the boot block lockout feature has been activated on
either block, the chip erase function will be disabled.
Absolute Maximum Ratings*
Temperature Under Bias................. -55°C to +125°C
Storage Temperature...................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground .............-0.6V to V
CC
+ 0.6V
Voltage on OE
with Respect to Ground ................... -0.6V to +13.5V
(continued)
*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
4-167
Device Operation
(Continued)
BOOT BLOCK LOCKOUT DETECTION:
A software
method is available to determine whether programming of
either boot block section is locked out. See Software Prod-
uct Identification Entry and Exit sections. When the device
is in the software product identification mode, a read from
location 00002H will show if programming the lower ad-
dress boot block is locked out while reading location
FFFF2H will do so for the upper boot block. If the data is
FE, the corresponding block can be programmed; if the
data is FF, the program lockout feature has been activated
and the corresponding block cannot be programmed. The
software product identification exit mode should be used
to return to standard operation.
DC and AC Operating Range
AT29C040A-12
Operating
Temperature (Case)
V
CC
Power Supply
Com.
Ind.
0°C - 70°C
-40°C - 85°C
5V
±
10%
AT29C040A-15
0°C - 70°C
-40°C - 85°C
5V
±
10%
AT29C040A-20
0°C - 70°C
-40°C - 85°C
5V
±
10%
Operating Modes
Mode
Read
Program
(2)
Standby/Write Inhibit
Program Inhibit
Program Inhibit
Output Disable
Product Identification
Hardware
Software
(5)
Notes: 1. X can be V
IL
or V
IH
.
2. Refer to AC Programming Waveforms.
3. V
H
= 12.0V
±
0.5V.
CE
V
IL
V
IL
V
IH
X
X
X
OE
V
IL
V
IH
X
(1)
X
V
IL
V
IH
WE
V
IH
V
IL
X
V
IH
X
X
Ai
Ai
Ai
X
I/O
D
OUT
D
IN
High Z
High Z
A1 - A18 = V
IL
, A9 = V
H
,
(3)
A0 = V
IL
A1 - A18 = V
IL
, A9 = V
H
,
(3)
A0 = V
IH
A0 = V
IL
A0 = V
IH
Manufacturer Code
(4)
Device Code
(4)
Manufacturer Code
(4)
Device Code
(4)
V
IL
V
IL
V
IH
4. Manufacturer Code: 1F, Device Code: A4
5. See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol
I
LI
I
LO
I
SB1
I
SB2
I
CC
V
IL
V
IH
V
OL
V
OH1
V
OH2
4-168
Parameter
Input Load Current
Output Leakage Current
V
CC
Standby Current CMOS
V
CC
Standby Current TTL
V
CC
Active Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output High Voltage CMOS
I
OL
= 2.1 mA
I
OH
= -400
µA
I
OH
= -100
µA;
V
CC
= 4.5V
2.4
4.2
2.0
.45
Condition
V
IN
= 0V to V
CC
V
I/O
= 0V to V
CC
CE = V
CC
- 0.3V to V
CC
CE = 2.0V to V
CC
f = 5 MHz; I
OUT
= 0 mA
Com.
Ind.
Min
Max
10
10
100
300
3
40
0.8
Units
µA
µA
µA
µA
mA
mA
V
V
V
V
V
AT29C040A
AT29C040A
AC Read Characteristics
AT29C040A-12
Symbol
t
ACC
t
CE (1)
t
OE (2)
t
DF (3, 4)
t
OH
Parameter
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
Output Hold from OE, CE or Address,
whichever occurred first
0
0
0
Min
Max
AT29C040A-15
Min
Max
AT29C040A-20
Min
Max
Units
ns
ns
ns
ns
ns
120
120
50
30
0
0
0
150
150
70
40
0
0
0
200
200
80
50
AC Read Waveforms
(1, 2, 3, 4)
Notes: 1. CE may be delayed up to t
ACC
- t
CE
after the address
transition without impact on t
ACC
.
2. OE may be delayed up to t
CE
- t
OE
after the falling
edge of CE without impact on t
CE
or by t
ACC
- t
OE
after an address change without impact on t
ACC
.
3. t
DF
is specified from OE or CE whichever occurs first
(C
L
= 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and Measurement Level
Output Test Load
t
R
, t
F
< 5 ns
Pin Capacitance
(f = 1 MHz, T = 25°C)
(1)
Typ
C
IN
C
OUT
Note:
Max
6
12
Units
pF
pF
Conditions
V
IN
= 0V
V
OUT
= 0V
4
8
1. This parameter is characterized and is not 100% tested.
4-169
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