HTSICH56; HTSICH48
HITAG S transponder IC
Rev. 3.0 — 12 October 2011
210330
Product short data sheet
COMPANY PUBLIC
1. General description
The HITAG product line is well known and established in the contactless identification
market.
Due to the open marketing strategy of NXP Semiconductors there are various
manufacturers well established for both the transponders / cards as well as the
Read/Write Devices. All of them supporting HITAG 1 and HITAG 2 transponder IC's. With
the new HITAG S family, this existing infrastructure is extended with the next generation of
IC’s being substantially smaller in mechanical size, lower in cost, offering more operation
distance and speed, but still being operated with the same reader infrastructure and
transponder manufacturing equipment.
One Protocol - two memory options.
The protocol and command structure for HITAG S is based on HITAG 1, including
anticollision algorithm.
Two different memory sizes are offered and can be operated using exactly the same
protocol.
•
HITAG S256 with 256 bit Total Memory Read/Write
•
HITAG S2048 with 2048 bit Total Memory Read/Write
2. Features and benefits
2.1 Features
Integrated Circuit for Contactless Identification Transponders and Cards
Integrated resonance capacitor of 210 pF with
5
% tolerance over full production
Frequency range 100 kHz to 150 kHz.
2.2 Protocol
Modulation Read/Write Device
Transponder: 100 % ASK and Binary Pulse Length
Coding
Modulation Transponder
Read/Write Device: Strong ASK modulation with
Anticollision, Manchester and Bi-phase Coding
Fast Anticollision Protocol for inventory tracking: 100 Tags in 3.2 seconds
Cyclic Redundancy Check (CRC)
Optional Transponder Talks First Modes with user defined data length
Temporary switch from Transponder Talks First into Reader Talks First Mode
NXP Semiconductors
HTSICH56; HTSICH48
HITAG S transponder IC
Data Rate Read/Write Device to Transponder: 5.2 kBit/s
Data Rates Transponder to Read/Write Device: 2 kBit/s, 4 kBit/s, 8 kBit/s
2.3 Memory
Two memory options (256 bit, 2048 bit)
Up to 100000 erase/write cycles
10 years non-volatile data retention
Secure Memory Lock functionality
2.4 Supported standards
Full compliant to ISO 11784/85 Animal ID
Targeted to operated on hardware infrastructure of new upcoming standards
ISO 14223 (Animal ID with anticollision and read/write functionality)
ISO 18000-2 (AIDC Techniques-RFID or Item Management)
Supports German Waste Management Standard and Pigeon Race Standard
2.5 Security features
32 bit Unique Identification Number (UID)
48 bit secret key based encrypted authentication
2.6 Delivery types
Sawn, gold - bumped 8” Wafer
Sawn, gold - megabumped 8” Wafer
Contactless Chip Card Module MOA2
I – Connect (Low Cost Flip Chip Package)
HVSON2
3. Applications
Animal Identification
Laundry Automation
Beer keg and gas cylinder logistic
Pigeon Race Sports
Brand Protection Applications
HTSICH56_48_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product short data sheet
COMPANY PUBLIC
Rev. 3.0 — 12 October 2011
210330
2 of 21
NXP Semiconductors
HTSICH56; HTSICH48
HITAG S transponder IC
4. Quick reference data
Table 1.
Symbol
t
ret
N
endu(W)
C
i
Quick reference data
Parameter
retention time
write endurance
input capacitance
between IN1 and IN2
HTSICxxxxxEW/x7
[1]
[2]
Typical ratings are not guaranteed. Values are at 25
C
.
Measured with Q
coil
= 20, L
coil
= 7.5 mH, optimal tuned to resonance circuit;
V
IN1-IN2
= 2 V (RMS)
[2]
Conditions
T
amb
55
C
Min
10
100000
Typ
[1]
Max
-
-
Unit
year
cycle
Wafer EEPROM characteristics
Interface characteristics
199
210
221
pF
5. Ordering information
Table 2.
Ordering information
Package
Name
HTSICH5601EW/V7
HTSICH4801EW/V7
HTSICC5601EW/C7
HTSICC4801EW/C7
HTSMOH5601EV
HTSMOH4801EV
HTSFCH5601EV/DH
HTSFCH4801EV/DH
HTSH5601ETK
Wafer
Wafer
Wafer
Wafer
PLLMC
[1]
PLLMC
[1]
FCP2
FCP2
HVSON2
Memory size
256 bit
2048 bit
256 bit
2048 bit
256 bit
2048 bit
256 bit
2048 bit
256 bit
Description
Au-bumped die on sawn wafer, inkless
Au-bumped die on sawn wafer, inkless
Au-megabumped die on sawn wafer,
inkless
Au-megabumped die on sawn wafer,
inkless
plastic leadless module carrier
package; 35 mm wide tape
plastic leadless module carrier
package; 35 mm wide tape
metal flip chip package; 2 leads;
35 mm wide tape
metal flip chip package; 2 leads;
35 mm wide tape
plastic thermal enhanced very thin
small outline package; no leads;
2 terminals; body 3
2
0.85 mm
plastic thermal enhanced very thin
small outline package; no leads;
2 terminals; body 3
2
0.85 mm
Version
-
-
-
-
SOT500-3
SOT500-3
SOT732-1
SOT732-1
SOT899-1
Type number
HTSH4801ETK
HVSON2
2048 bit
SOT899-1
[1]
This package is also known as MOA2
HTSICH56_48_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product short data sheet
COMPANY PUBLIC
Rev. 3.0 — 12 October 2011
210330
3 of 21
NXP Semiconductors
HTSICH56; HTSICH48
HITAG S transponder IC
6. Block diagram
The HITAG S Transponder requires no external power supply. The contactless interface
generates the power supply and the system clock via the resonant circuitry by inductive
coupling to the Read/Write Device (RWD). The interface also demodulates data
transmitted from the RWD to the HITAG S Transponder, and modulates the magnetic field
for data transmission from the HITAG S Transponder to the RWD.
Data are stored in a non-volatile memory (EEPROM). The EEPROM has a capacity up to
2048 bit and is organized in 64 Pages consisting of 4 Bytes each (1 Page = 32 Bits).
ANALOGUE
RF INTERFACE
VREG
PAD
VDD
DIGITAL CONTROL
EEPROM
ANTICOLLISION
RECT
DEMOD
data
in
READ/WRITE
CONTROL
TRANSPONDER
Cres
MOD
data
out
ACCESS CONTROL
256-bit
or
2048-bit
EEPROM INTERFACE
CONTROL
CLK
PAD
clock
RF INTERFACE
CONTROL
R/W
SEQUENCER
CHARGE PUMP
001aak208
Fig 1.
Block diagram
HTSICH56_48_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product short data sheet
COMPANY PUBLIC
Rev. 3.0 — 12 October 2011
210330
4 of 21
NXP Semiconductors
HTSICH56; HTSICH48
HITAG S transponder IC
7. Functional description
7.1 Memory organization
Page
Address
Block 0
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x3B
0x3C
0x3D
0x3E
0x3F
HITAG S Type
32 bit
page 0
page 1
page 2
page 3
page 4
page 5
page 6
page 7
page 8
page 9
page 10
page 11
page 12
page 13
page 14
page 15
page 16
page 59
page 60
page 61
page 62
page 63
H56
H48
Block 1
Block 2
Block 3
Block 15
aaa-000830
Fig 2.
Memory organization
The EEPROM has a capacity up to 2048 bit and is organized in 16 Blocks, consisting of
4 Pages each, for commands with Block access. A Page consists of 4 Bytes each (1 Page
= 32 Bits) and is the smallest access unit.
Addressing is done Page by Page (Page 0 to 63) and access is gained either Page by
Page or Block by Block entering the respective Page start address. In case of Block
Read/Write access, the transponder is processed from the start Page address within one
block to the end of the corresponding block.
Two different types of HITAG S IC’s with different memory sizes as shown in the figure
above are available.
7.2 HITAG S plain mode
Table 3.
Memory map for HITAG S in plain mode
MSByte
page address
0x00
MSB
UID3
LSB MSB
UID2
LSB MSB
UID1
LSByte
LSB MSB
UID0
LSB
HTSICH56_48_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product short data sheet
COMPANY PUBLIC
Rev. 3.0 — 12 October 2011
210330
5 of 21
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