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5962R9662103V9A

Description
4000/14000/40000 SERIES, TRIPLE 3-INPUT NAND GATE, UUC14, DIE-14
Categorylogic    logic   
File Size108KB,9 Pages
ManufacturerRenesas Electronics Corporation
Websitehttps://www.renesas.com/
Download Datasheet Parametric Compare View All

5962R9662103V9A Overview

4000/14000/40000 SERIES, TRIPLE 3-INPUT NAND GATE, UUC14, DIE-14

5962R9662103V9A Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?incompatible
Parts packaging codeDIE
package instructionDIE, DIE OR CHIP
Contacts14
Reach Compliance Codecompliant
series4000/14000/40000
JESD-30 codeR-XUUC-N14
JESD-609 codee0
Load capacitance (CL)50 pF
Logic integrated circuit typeNAND GATE
Number of functions3
Number of entries3
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialUNSPECIFIED
encapsulated codeDIE
Encapsulate equivalent codeDIE OR CHIP
Package shapeRECTANGULAR
Package formUNCASED CHIP
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5/15 V
Prop。Delay @ Nom-Sup338 ns
propagation delay (tpd)338 ns
Certification statusNot Qualified
Schmitt triggerNO
Filter levelMIL-PRF-38535 Class V
Maximum supply voltage (Vsup)18 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTIN LEAD
Terminal formNO LEAD
Terminal locationUPPER
Maximum time at peak reflow temperatureNOT SPECIFIED
total dose100k Rad(Si) V
Base Number Matches1
CD4011BMS, CD4012BMS
CD4023BMS
November 1994
CMOS NAND Gates
Pinouts
CD4011BMS
TOP VIEW
Features
• High-Voltage Types (20V Rating)
• Propagation Delay Time = 60ns (typ.) at CL = 50pF,
VDD = 10V
• Buffered Inputs and Outputs
• Standardized Symmetrical Output Characteristics
A 1
B 2
J = AB 3
14 VDD
13 H
12 G
11 M = GH
10 L = EF
9 E
8 F
• Maximum Input Current of 1µA at 18V Over Full Package-
Temperature Range; 100nA at 18V and +25
o
C
• 100% Tested for Maximum Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
K = CD 4
C 5
D 6
VSS 7
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Stan-
dards No. 13B, “Standard Specifications for Descrip-
tion of “B” Series CMOS Device’s
J = ABCD 1
A 2
B 3
CD4012BMS
TOP VIEW
14 VDD
13 K = EFGH
12 H
11 G
10 F
9 E
8 NC
NC = NO CONNECTION
Description
CD4011BMS - Quad 2 Input
CD4012BMS - Dual 4 Input
CD4023BMS - Triple 3 Input
CD4011BMS, CD4012BMS, and CD4023BMS NAND gates
provide the system designer with direct implementation of
the NAND function and supplement the existing family of
CMOS gates. All inputs and outputs are buffered.
The CD4011BMS, CD4012BMS and the CD4023BMS is
supplied in these 14 lead outline packages:
CD4011B
CD4012B
H4H
H1B
H3W
CD4023B
H4Q
H1B
H3W
C 4
D 5
NC 6
VSS 7
CD4023BMS
TOP VIEW
A 1
B 2
D 3
E 4
F 5
K = DEF 6
VSS 7
14 VDD
13 G
12 H
11 I
10 L = GHI
9 J = ABC
8 C
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4Q
H1B
H3W
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
File Number
3079
7-53

5962R9662103V9A Related Products

5962R9662103V9A 5962R9662103VXC 5962R9662103VCC
Description 4000/14000/40000 SERIES, TRIPLE 3-INPUT NAND GATE, UUC14, DIE-14 4000/14000/40000 SERIES, TRIPLE 3-INPUT NAND GATE, CDFP14, CERAMIC, DFP-14 4000/14000/40000 SERIES, TRIPLE 3-INPUT NAND GATE, CDIP14, CERAMIC, DIP-14
Parts packaging code DIE DFP DIP
package instruction DIE, DIE OR CHIP DFP, FL14,.3 DIP, DIP14,.3
Contacts 14 14 14
Reach Compliance Code compliant compli compliant
series 4000/14000/40000 4000/14000/40000 4000/14000/40000
JESD-30 code R-XUUC-N14 R-CDFP-F14 R-CDIP-T14
JESD-609 code e0 e4 e4
Load capacitance (CL) 50 pF 50 pF 50 pF
Logic integrated circuit type NAND GATE NAND GATE NAND GATE
Number of functions 3 3 3
Number of entries 3 3 3
Number of terminals 14 14 14
Maximum operating temperature 125 °C 125 °C 125 °C
Minimum operating temperature -55 °C -55 °C -55 °C
Package body material UNSPECIFIED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED
encapsulated code DIE DFP DIP
Encapsulate equivalent code DIE OR CHIP FL14,.3 DIP14,.3
Package shape RECTANGULAR RECTANGULAR RECTANGULAR
Package form UNCASED CHIP FLATPACK IN-LINE
power supply 5/15 V 5/15 V 5/15 V
propagation delay (tpd) 338 ns 338 ns 338 ns
Certification status Not Qualified Not Qualified Not Qualified
Schmitt trigger NO NO NO
Filter level MIL-PRF-38535 Class V MIL-PRF-38535 Class V MIL-PRF-38535 Class V
Maximum supply voltage (Vsup) 18 V 18 V 18 V
Minimum supply voltage (Vsup) 3 V 3 V 3 V
Nominal supply voltage (Vsup) 5 V 5 V 5 V
surface mount YES YES NO
technology CMOS CMOS CMOS
Temperature level MILITARY MILITARY MILITARY
Terminal surface TIN LEAD GOLD GOLD
Terminal form NO LEAD FLAT THROUGH-HOLE
Terminal location UPPER DUAL DUAL
total dose 100k Rad(Si) V 100k Rad(Si) V 100k Rad(Si) V
Base Number Matches 1 1 1
Prop。Delay @ Nom-Sup 338 ns - 338 ns
length - 9.525 mm 19.43 mm
MaximumI(ol) - 0.00064 A 0.00064 A
Maximum seat height - 2.92 mm 5.08 mm
Terminal pitch - 1.27 mm 2.54 mm
width - 6.285 mm 7.62 mm

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