V 1, V 2 V 1, V 2 6.0 V ; AGND = DGND = AGND = DGND = 0 V; T = T to T unless
DD
DD
DD
DD
P
P
RF
RF
IF
IF
A
MIN
MAX
1
10%, 5 V
10%;
P
arameter
RF/IF CHARACTERISTICS (3 V)
RF Input Frequency (RF
IN
)
ADF4216
ADF4217
ADF4218
IF Input Frequency (IF
IN
)
RF Input Sensitivity
IF Input Sensitivity
Maximum Allowable
Prescaler Output Frequency
3
RF/IF CHARACTERISTICS (5 V)
RF Input Frequency (RF
IN
)
ADF4216
ADF4217
ADF4218
IF Input Frequency (IF
IN
)
RF Input Sensitivity
IF Input Sensitivity
Maximum Allowable
Prescaler Output Frequency
3
REFIN CHARACTERISTICS
REFIN Input Frequency
REFIN Input Sensitivity
4
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency
5
CHARGE PUMP
I
CP
Sink/Source
High Value
Low Value
Absolute Accuracy
I
CP
Three-State Leakage Current
Sink and Source Current Matching
I
CP
vs. V
CP
I
CP
vs. Temperature
LOGIC INPUTS
V
INH
, Input High Voltage
V
INL
, Input Low Voltage
I
INH
/I
INL
, Input Current
C
IN
, Input Capacitance
Oscillator Input Current
LOGIC OUTPUTS
V
OH
, Output High Voltage
V
OL
, Output Low Voltage
POWER SUPPLIES
V
DD
1
V
DD
2
V
P
B Version
B Chips
2
Unit
Test Conditions/Comments
See Figure 3 for Input Circuit.
For lower frequency operation (below the
minimum stated) use a square wave source.
0.2/1.2
0.2/2.0
0.5/2.5
45/550
–15/+4
–10/+4
165
0.2/1.2
0.2/2.0
0.5/2.5
45/550
–15/+4
–10/+4
165
GHz min/max
GHz min/max
GHz min/max
MHz min/max
dBm min/max
dBm min/max
MHz max
0.2/1.2
0.2/2.0
0.5/2.5
25/550
–15/+4
–10/+4
200
5/40
0.5
10
±
100
40
0.2/1.2
0.2/2.0
0.5/2.5
25/550
–15/+4
–10/+4
200
5/40
0.5
10
±
100
40
GHz min/max
GHz min/max
GHz min/max
MHz min/max
dBm min/max
dBm min/max
MHz max
MHz min/max
V p-p min
pF max
µA
max
MHz max
See Figure 3 for Input Circuit.
For lower frequency operation (below the
minimum stated) use a square wave source.
For f < 5 MHz, use dc-coupled square wave
(0 to V
DD
).
AC-Coupled. When DC-Coupled:
0 to V
DD
max (CMOS-Compatible)
4.5
1.125
1
1
1
10
10
0.8
×
V
DD
0.2
×
V
DD
±
1
10
±
100
V
DD
– 0.4
0.4
2.7/5.5
V
DD
1
V
DD
1/6.0
4.5
1.125
1
1
1
10
10
0.8
×
V
DD
0.2
×
V
DD
±
1
10
±
100
V
DD
– 0.4
0.4
2.7/5.5
V
DD
1
V
DD
1/6.0
mA typ
mA typ
% typ
nA typ
% typ
% max
% typ
V min
V max
µA
max
pF max
µA
max
V min
V max
V min/V max
V min/V max
0.5 V V
CP
V
CP
= V
P
/2
V
P
– 0.5 V
I
OH
= 500
µA
I
OL
= 500
µA
AV
DD
V
P
6.0 V
–2–
REV. 0
ADF4216/ADF4217/ADF4218
Parameter
POWER SUPPLIES (Continued)
I
DD
(RF + IF)
6
ADF4216
ADF4217
ADF4218
I
DD
(RF Only)
ADF4216
ADF4217
ADF4218
I
DD
(IF Only)
ADF4216
ADF4217
ADF4218
I
P
(I
P
1 + I
P
2)
Low-Power Sleep Mode
NOISE CHARACTERISTICS
Phase Noise Floor
7
Phase Noise Performance
8
ADF4216, ADF4217, ADF4218 (IF)
9
ADF4216 (RF): 900 MHz Output
10
ADF4217 (RF): 900 MHz Output
10
ADF4218 (RF): 900 MHz Output
10
ADF4216 (RF): 836 MHz Output
11
ADF4217 (RF): 1750 MHz Output
12
ADF4217 (RF): 1750 MHz Output
13
ADF4218 (RF): 1960 MHz Output
14
Spurious Signals
ADF4216 ADF4217, ADF4218 (IF)
9
ADF4216 (RF): 900 MHz Output
10
ADF4217 (RF): 900 MHz Output
10
ADF4218 (RF): 900 MHz Output
10
ADF4216 (RF): 836 MHz Output
11
ADF4217 (RF): 1750 MHz Output
12
ADF4217 (RF): 1750 MHz Output
13
ADF4218 (RF): 1960 MHz Output
14
B Version
B Chips
2
Unit
Test Conditions/Comments
See TPC 22 and TPC 23
9.0 mA typical at V
DD
= 3 V and T
A
= 25°C
12 mA typical at V
DD
= 3 V and T
A
= 25°C
14 mA typical at V
DD
= 3 V and T
A
= 25°C
5.0 mA typical at V
DD
= 3 V and T
A
= 25°C
7.0 mA typical at V
DD
= 3 V and T
A
= 25°C
9.0 mA typical at V
DD
= 3 V and T
A
= 25°C
4.5 mA typical at V
DD
= 3 V and T
A
= 25°C
4.5 mA typical at V
DD
= 3 V and T
A
= 25°C
4.5 mA typical at V
DD
= 3 V and T
A
= 25°C
T
A
= 25°C
0.5
µA
typical
@ 25 kHz PFD Frequency
@ 200 kHz PFD Frequency
@ VCO Output
@ 1 kHz Offset and 200 kHz PFD Frequency
@ 1 kHz Offset and 200 kHz PFD Frequency
@ 1 kHz Offset and 200 kHz PFD Frequency
@ 1 kHz Offset and 200 kHz PFD Frequency
@ 300 Hz Offset and 30 kHz PFD Frequency
@ 1 kHz Offset and 200 kHz PFD Frequency
@ 200 Hz Offset and 10 kHz PFD Frequency
@ 1 kHz Offset and 200 kHz PFD Frequency
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
@ 30 kHz/60 kHz and 30 kHz PFD Frequency
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
@ 10 kHz/20 kHz and 10 kHz PFD Frequency
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
18
21
25
10
14
18
9
9
9
0.6
5
–171
–164
–91
–87
–88
–90
–78
–85
–66
–84
–97/–106
–98/–106
–91/–100
–80/–84
–80/–84
–88/–90
–65/–73
–80/–84
9
12
14
5
7
9
4.5
4.5
4.5
0.6
5
–171
–164
–91
–87
–88
–90
–78
–85
–66
–84
–97/–106
–98/–106
–91/–100
–80/–84
–80/–84
–88/–90
–65/–73
–80/–84
mA max
mA max
mA max
mA max
mA max
mA max
mA max
mA max
mA max
mA max
µA
max
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dB typ
dB typ
dB typ
dB typ
dB typ
dB typ
dB typ
dB typ
NOTES
1
Operating temperature range is as follows: B Version: –40°C to +85°C.
2
The B Chip specifications are given as typical values.
3
This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the IF/RF input is divided down to a frequency that is
less than this value.
4
V
DD
1 = V
DD
2 = 3 V; For V
DD
1 = V
DD
2 = 5 V, use CMOS-compatible levels.
5
Guaranteed by design. Sample tested to ensure compliance.
6
P = 16; RF
IN
= 900 MHz; IF
IN
= 540 MHz.
7
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value).
8
The phase noise is measured with the EVAL-ADF421XEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the
synthesizer (f
REFOUT
= 10 MHz @ 0 dBm).
9
f
REFIN
= 10 MHz; f
PFD
= 200 kHz; Offset frequency = 1 kHz; f
IF
= 540 MHz; N = 2700; Loop B/W = 20 kHz.
10
f
REFIN
= 10 MHz; f
PFD
= 200 kHz; Offset frequency = 1 kHz; f
RF
= 900 MHz; N = 4500; Loop B/W = 20 kHz.
11
f
REFIN
= 10 MHz; f
PFD
= 30 kHz; Offset frequency = 300 Hz; f
RF
= 836 MHz; N = 27867; Loop B/W = 3 kHz.
12
f
REFIN
= 10 MHz; f
PFD
= 200 kHz; Offset frequency = 1 kHz; f
RF
= 1750 MHz; N = 8750; Loop B/W = 20 kHz.
13
f
REFIN
= 10 MHz; f
PFD
= 10 kHz; Offset frequency = 200 Hz; f
RF
= 1750 MHz; N = 175000; Loop B/W = 1 kHz.
14
f
REFIN
= 10 MHz; f
PFD
= 200 kHz; Offset frequency = 1 kHz; f
RF
= 1960 MHz; N = 9800; Loop B/W = 20 kHz.
Specifications subject to change without notice.
REV. 0
–3–
ADF4216/ADF4217/ADF4218
TIMING CHARACTERISTICS
Parameter
t
1
t
2
t
3
t
4
t
5
t
6
Limit at
T
MIN
to T
MAX
(B Version)
10
10
25
25
10
20
(V
DD
1 = V
DD
2 = 3 V 10%, 5 V 10%; V
P
1, V
P
2 = V
DD
, 5 V
T
A
= T
MIN
to T
MAX
unless otherwise noted.)
10%; AGND = DGND = 0 V;
Unit
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
DATA to CLOCK Setup Time
DATA to CLOCK Hold Time
CLOCK High Duration
CLOCK Low Duration
CLOCK to LE Setup Time
LE Pulsewidth
NOTES
Guaranteed by design but not production tested.
Specification subject to change without notice.
t
3
CLOCK
t
4
t
1
DATA
DB21 (MSB)
DB20
t
2
DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t
6
LE
LE
t
5
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS
1, 2
(T
A
= 25°C unless otherwise noted)
V
DD
1 to GND
3
. . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
DD
1 to V
DD
2 . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
V
P
1, V
P
2 to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
P
1, V
P
2 to V
DD
1 . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V
Digital I/O Voltage to GND . . . . . . –0.3 V to DV
DD
+ 0.3 V
Analog I/O Voltage to GND . . . . . . . . . –0.3 V to V
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