336LD-FREQ datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> oscillator> 336LD-FREQ

336LD-FREQ: DescriptionPECL Output Clock Oscillator, 10MHz Min, 200MHz Max; CategoryPassive components oscillator; File Size148KB，2 Pages; ManufacturerCTS

Download Datasheet Parametric View All

336LD-FREQ Overview

PECL Output Clock Oscillator, 10MHz Min, 200MHz Max

336LD-FREQ Parametric

Parameter Name	Attribute value
Reach Compliance Code	unknown
Other features	ENABLE/DISABLE FUNCTION
Maximum control voltage	3.3 V
Minimum control voltage
maximum descent time	1.5 ns
Frequency Adjustment - Mechanical	NO
Frequency offset/pull rate	100 ppm
frequency stability	20%
linearity	10%
Manufacturer's serial number	336
Installation features	SURFACE MOUNT
Maximum operating frequency	200 MHz
Minimum operating frequency	10 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	PECL
Output load	50 OHM
physical size	20.57mm x 13.84mm x 5.71mm
longest rise time	1.5 ns
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Base Number Matches	1

Preview

Download Datasheet

View All

Preliminary Specification

Rev. X02

Model 336

“AnyDrive™ ” Series

Precision HFF VCXO

♦

Versatile Differential Output Stage

♦

PECL, LVDS, ECL, CMOS, CML, Sine

♦

Very Low Phase Jitter: < 0.5 pSec

♦

+3.3Vdc or +5.0Vdc Operation

♦

High Freq. Fundamental AT Crystal

♦

Proprietary Low Aging Inverted Mesa

♦

Output Enable Function

♦

Low Phase Noise

♦

Guaranteed Minimum Pull Range

Electrical Characteristics

Parameter

Power

Requirements

Power Supply

Supply Current

Frequency

Stabilities

Center

Frequency

Sym

Vcc

Icc

Conditions

336L

336S

Vcc=Max. (3.3Vdc)

50Ω . Load (5.0Vdc)

Min

3.135

4.75

Typical

3.30

5.0

Max

3.465

5.25

Unit

Vdc

nom

155.52

77.760

38.88

19.44

200

MHz

Initial Tolerance

Freq. vs. Temp.

Freq. vs. Voltage

Freq. vs. Load

Freq. vs Time

(Aging)

Deviation

Characteristics

Control Voltage

Frequency

Deviation

Linearity

Absolute Pull

Range

cal

∆f/∆Temp

∆f/∆Vcc

∆f/∆RL

∆f/∆Time

Ta=+25°C

EFC=0.5Vcc

-10

+10

ppm

Vcc

10% Variation

20 years

0.5

∆f

Lin

APR

3.3V “ Version

L”

5.0V “ Version

S”

+25°C at time of

Shipment

Best Staight Line

Fit

Under all

conditions for the

life of the part (Ref.

to f

nom

)

-3db Point

0.0

-10

3.3

5.0

100

ppm

Input Impedance

Bandwidth

Waveform

Parameters

Symmetry

Amplitude

Rise/Fall Times

Load

Phase Jitter

Phase Noise

Zin

KΩ

KHz

Sym

tr, tf

@ 50% Level

50Ω Load

20% to 80%

Output to Ground

12KHz to 20MHz

Bandwidth

1KHz

10KHz

0.200

0.250

1.5

<0.5

Vp-p

nSec

Ω

pSec RMS

dBc/Hz

-112

-145

♦ ♦ ♦

CTS Frequency Products

♦

400 W. North Street

♦

Carlisle, PA 17013

♦

717-243-5929

♦ ♦ ♦

Recommended Resources

Fixed and switching hybrid regulated power supply electronic circuit diagram

Interface circuit between power supply coupler and relay

AC induced voltage suppression circuit

Active high power factor correction pre-regulator circuit diagram using UC3852

Combustible gas leakage degree display alarm (1)

Computer motherboard circuit diagram 820 1_64

LCD1602 backlight has no effect: [font=微软雅黑][size=5]I need help from you guys. My development board is EP2C8Q208C8. I learned verylog. The store only gave me a vhdl version of the experimental routine, so I used my classmate's progra...; renee FPGA/CPLD

Please ask a question: Try to write out the data structure of the following figure in big-endian and little-endian machines. In the figure below, a and b occupy 4 bits in length. 0 0 1 2 3 4 5 6 7 +-+-+-+-+-+-+-+-+ | | | | ...; mooddog Embedded System

Could you please tell me what this code means?: This code was given to me by my teacher. It was written in the bulkloop framework using keil uvision2 software. void DA5384(unsigned char indata) { unsigned char i; unsigned int mydata; unsigned int d...; hlw0510940108 Embedded System

The weather is too hot to run.: The sun is shining brightly at 8 o'clock. If I keep running like this, I will feel like I'm in Africa. So, starting from tomorrow morning, I will go to Beihang Green Park to jump rope. I have been nea...; soso Talking

The formation of GAP and memory control issues (single chip microcomputer) attached map file: #includebit b1,b2; bdata char bx,by; xdata char zz; pdata char buf[100]; void main (void) { { b1=0; b2=1; bx=12; by=26; while (1) P5 =P4; } /**************************Part of the MAP file: LINK MAP OF...; 0442323 Embedded System

Can someone explain a low pass filter example? I don't understand the question mark!: This section uses an example to illustrate the method of converting a C program from floating point to fixed point. This is a C language program that performs low-pass filtering on a speech signal (0....; wdwxn Analogue and Mixed Signal

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components