UC1525B-SP
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SLUS874 – JANUARY 2009
RAD-TOLERANT CLASS-V REGULATING PULSE WIDTH MODULATOR
1
FEATURES
QML-V Qualified, SMD 5962-89511
Rad-Tolerant: 30 kRad (Si) TID
(1)
8-V to 35-V Operation
5.1-V Buried Zener Reference Trimmed to
±0.75%
100-Hz to 400-kHz Oscillator Range
Separate Oscillator Sync Terminal
Adjustable Deadtime Control
Internal Soft Start
Pulse-by-Pulse Shutdown
Input Undervoltage Lockout With Hysteresis
Latching PWM to Prevent Multiple Pulses
Dual Source/Sink Output Drivers
Low Cross Conduction Output Stage
Tighter Reference Specifications
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DESCRIPTION
The UC1525B pulse width modulator integrated
circuit is designed to offer improved performance and
lowered external parts count when used in designing
all types of switching power supplies. The on-chip
5.1-V buried zener reference is trimmed to ±0.75%,
and the input common-mode range of the error
amplifier includes the reference voltage, eliminating
external resistors. A sync input to the oscillator allows
multiple units to be slaved or a single unit to be
synchronized to an external system clock. A single
resistor between the CT and the discharge terminals
provide a wide range of dead-time adjustment. These
devices also feature built-in soft-start circuitry with
only an external timing capacitor required. A
shutdown terminal controls both the soft-start circuitry
and the output stages, providing instantaneous turn
off through the PWM latch with pulsed shutdown, as
well as soft-start recycle with longer shutdown
commands. These functions are also controlled by an
undervoltage lockout which keeps the outputs off and
the soft-start capacitor discharged for sub-normal
input voltages. This lockout circuitry includes
approximately 500 mV of hysteresis for jitter-free
operation. Another feature of these PWM circuits is a
latch following the comparator. Once a PWM pulse
has been terminated for any reason, the outputs
remain off for the duration of the period. The latch is
reset with each clock pulse. The output stages are
totem-pole designs capable of sourcing or sinking in
excess of 200 mA. The UC1525B output stage
features NOR logic, giving a LOW output for an OFF
state.
(1)
Radiation tolerance is a typical value based upon initial device
qualification with dose rate = 10 mrad/sec. Radiation Lot
Acceptance Testing is available - contact factory for details.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
UC1525B-SP
SLUS874 – JANUARY 2009...............................................................................................................................................................................................
www.ti.com
BLOCK DIAGRAM
This device has limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
(1)
T
A
–55°C to 125°C
(1)
(2)
PACKAGE
(2)
FK
ORDERABLE PART NUMBER
5962-8951106V2A
TOP-SIDE MARKING
UC1525BFK-SP
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at
www.ti.com.
Package drawings, thermal data, and symbolization are available at
www.ti.com/packaging.
2
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UC1525B-SP
Copyright © 2009, Texas Instruments Incorporated
UC1525B-SP
www.ti.com...............................................................................................................................................................................................
SLUS874 – JANUARY 2009
ABSOLUTE MAXIMUM RATINGS
(1) (2)
over operating free-air temperature range (unless otherwise noted)
+V
IN
V
C
V
I
I
O
Supply voltage
Collector supply voltage
Logic inputs
Analog inputs
Output current, source or sink
Reference output current
Oscillator charging current
P
D
T
J
T
stg
T
lead
(1)
(2)
Power dissipation
Operating junction temperature
Storage temperature range
Lead temperature (soldering, 10 seconds)
T
A
= 25°C
T
C
= 25°C
40 V
40 V
–0.3 V to 5.5 V
–0.3 V to V
IN
500 mA
50 mA
5 mA
1000 mW
2000 mW
–55°C to 150°C
–65°C to 150°C
300°C
Stresses beyond those listed under
absolute maximum ratings
may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under
recommended operating
conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to ground. Currents are positive into, negative out of the specified terminal.
RECOMMENDED OPERATING CONDITIONS
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
+V
IN
V
C
Input voltage
Collector supply voltage
Sink/source load current (steady state)
Sink/source load current (peak)
Reference load current
Oscillator frequency range
Oscillator timing resistor
Oscillator timing capacitor
Dead time resistor range
(1)
Range over which the device is functional and parameter limits are specified.
8
4.5
0
0
0
0.1
2
0.001
0
MAX
35
35
100
400
20
400
150
0.1
500
UNIT
V
V
mA
mA
mA
kHz
kΩ
µF
Ω
Copyright © 2009, Texas Instruments Incorporated
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UC1525B-SP
3
UC1525B-SP
www.ti.com...............................................................................................................................................................................................
SLUS874 – JANUARY 2009
ELECTRICAL CHARACTERISTICS (continued)
V
IN
= 20 V, T
A
= T
J
= –55°C to 125°C (unless otherwise noted)
PARAMETER
Error Amplifier Section (V
CM
= 5.1 V)
Input offset voltage
Input bias current
Input offset current
DC open loop gain
Gain-bandwidth product
Ouput low level
Output high level
Common mode rejection
Supply voltage rejection
PWM Comparator
Minimum duty cycle
Maximum duty cycle
Input threshold
(4)
Input threshold
(4)
(4)
(3)
TEST CONDITIONS
MIN
TYP
0.5
1
MAX
5
10
1
UNIT
mV
µA
µA
dB
MHz
R
L
≥
10 MΩ
A
V
= 0 dB, T
J
= 25°C
60
1
3.8
75
2
0.2
5.6
75
60
0
0.5
V
V
dB
dB
%
%
V
V
CM
= 1.5 V to 5.2 V
V
IN
= 8 V to 35 V
60
50
45
Zero duty cycle
Maximum duty cycle
0.7
49
0.9
3.3
0.05
3.6
V
µA
Input bias current
Shutdown Section
Soft start current
Soft start low level
Shutdown threshold
Shutdown input current
Shutdown delay
(3)
Output Drivers (Each OUtput) (V
C
= 20 V)
Output low level
Output high level
Undervoltage lockout
Collector leakage
Rise time
(3)
V
SHUTDOWN
= 0 V, V
SOFTSTART
= 0 V
V
SHUTDOWN
= 2.5 V
To outputs, V
SOFTSTART
= 5.1 V, T
J
= 25°C
V
SHUTDOWN
= 2.5 V
V
SHUTDOWN
= 2.5 V, T
J
= 25°C
I
SINK
= 20 mA
I
SINK
= 100 mA
I
SOURCE
= 20 mA
I
SOURCE
= 100 mA
V
COMP
and V
SOFTSTART
= High
V
C
= 35 V
C
L
= 1 nF, T
J
= 25°C
C
L
= 1 nF, T
J
= 25°C
Per cycle, T
J
= 25°C
V
IN
= 35 V
25
0.6
50
0.4
0.8
0.4
0.2
0.2
1
80
0.7
1
1
0.5
0.4
2
µA
V
V
mA
µs
V
V
18
17
6
19
18
7
100
50
30
14
20
8
200
600
300
V
µA
ns
ns
nc
mA
Fall time
(3)
Cross conduction charge
Total Standby Current
Supply current
(3)
(4)
Parameters ensured by design and/or characterization, if not production tested.
Tested at f
osc
= 40 kHz (R
T
= 3.6 kΩ, C
T
= 0.01
µF,
R
D
= 0
Ω).
Approximate oscillator frequency is defined by: f = 1/(C
T
(0.7 x R
T
+ 3R
D
)).
Copyright © 2009, Texas Instruments Incorporated
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