EEWORLDEEWORLDEEWORLD

Part Number

Search

3GW8E-30N-FREQ

Description
LVCMOS Output Clock Oscillator, 200.1MHz Min, 800MHz Max, ROHS COMPLIANT, DIP-8/4
CategoryPassive components    oscillator   
File Size86KB,1 Pages
ManufacturerEuroquartz
Websitehttp://www.euroquartz.co.uk/
Environmental Compliance
Download Datasheet Parametric View All

3GW8E-30N-FREQ Overview

LVCMOS Output Clock Oscillator, 200.1MHz Min, 800MHz Max, ROHS COMPLIANT, DIP-8/4

3GW8E-30N-FREQ Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
Reach Compliance Codecompliant
Maximum control voltage1.85 V
Minimum control voltage1.45 V
Frequency Adjustment - MechanicalNO
Frequency offset/pull rate30 ppm
frequency stability50%
linearity10%
Installation featuresTHROUGH HOLE MOUNT
Maximum operating frequency800 MHz
Minimum operating frequency200.1 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeLVCMOS
Output load15 pF
physical size12.8mm x 12.8mm x 5.08mm
Maximum supply voltage3.465 V
Minimum supply voltage3.135 V
Nominal supply voltage3.3 V
surface mountNO
maximum symmetry55/45 %
Base Number Matches1
EURO
QUARTZ
8 pin Dual-in-Line
Frequency range 200.1MHz to 800MHz
LVCMOS Output
Supply Voltage 3.3 VDC
High Q fundamental mode crystal
Low jitter multiplier circuit
DESCRIPTION
OUTLINE & DIMENSIONS
GW42 VCXOs, are packaged in an industry-standard, 4 pad, 11.4mm
x 9.6mm x 2.5mm SMD package. GW42 VCXOs incorporate a high Q
fundamental crystal and a low jitter multiplier circuit.
SPECIFICATION
Frequency Range:
Supply Voltage:
Output Logic:
Integrated Phase Jitter:
Period Jitter RMS:
Period Jitter Peak to peak:
Phase Noise:
Initial Frequency Accuracy:
Output Voltage HIGH (1):
Output Voltage LOW (0):
Pulling Range:
Temperature Stability:
Output Load:
Start-up Time:
Duty Cycle:
Rise/Fall Times:
Current Consumption
<96MHz:
>96MHz:
Linearity:
Modulation Bandwidth:
Input Impedance:
Slope Polarity:
(Transfer function)
GW8 VCXO
200.1MHz ~ 800.0MHz
200.1MHz to 800.0MHz
3.3 VDC ±5%
LVCMOS
2.6ps typical, 4.0ps maximum
(for 155.250MHz)
4.3ps typical (for 155.250MHz)
27.0ps typical (for 155.250MHz)
See table below
Tune to the nominal frequency
with Vc= 1.65 ±0.2VDC
90% Vdd minimum
10% Vdd maximum
From ±30ppm to ±150ppm
See table
15pF
10ms maximum, 5ms typical
50% ±5% measured at 50% Vdd
1.2ns typical (15pF load)
30mA maximum (15pF load)
40mA maximum (15pF load)
10% maximum, 6% typical
25kHz minimum
2 MW minimum
Monotonic and Positive. (An
increase of control voltage
always increases output
frequency.)
-50° to +100°C
±5ppm per year maximum
Not available (4
pad package)
Fully compliant
PHASE NOISE
10Hz
100Hz
1kHz
10kHz
100kHz
1MHz
10MHz
-65dBc/Hz
-95dBc/Hz
-120dBc/Hz
-125dBc/Hz
-121dBc/Hz
-120dBc/Hz
-140dBc/Hz
Storage Temperature:
Ageing:
Enable/Disable (Tristate):
RoHS Status:
FREQUENCY STABILITY
Stability Code Stability ±ppm Temp. Range
A
25
0°~+70°C
B
50
0°~+70°C
C
100
0°~+70°C
D
25
-40°~+85°C
E
50
-40°~+85°C
F
100
-40°~+85°C
If non-standard frequency stability is required
Use ‘I’ followed by stability, i.e. I20 for ±20ppm
PART NUMBERING
Example:
3GW8B-80N-250.00
Supply Voltage
3 = +3.3V
Series Designator
GW8
Stability over temperature range
(See table)
Pullability in ±ppm
Pullability determinator
N = minimum
M = maximum
T = Typical
Frequency in MHz
EUROQUARTZ LIMITED Blacknell Lane CREWKERNE Somerset UK TA18 7HE
Tel: +44 (0)1460 230000 Fax: +44 (0)1460 230001 info@euroquartz.co.uk www.euroquartz.co.uk
Share a picture of domestic alternative power IC
A picture of domestic alternative power IC...
Jacktang Domestic Chip Exchange
The truth about the embedded industry outlook
[size=4]Embedded technology is everywhere, from portable MP3, language repeater, mobile phone, PDA to smart TV, smart refrigerator, set-top box in the home, to robots in industrial production and ente...
程序天使 Robotics Development
51 MCU classic data and routines
Publish some classic information about 51 single-chip microcomputers. After reading them, you will master them....
echowjk 51mcu
Debugging FPGAs with the SignalTap II Logic Analyzer.pdf
Debugging FPGAs with the SignalTap II Logic Analyzer.pdf...
呱呱 PCB Design
How to play AVI in EVC4.0? Can anyone give me some ideas?
As the title says, you can also play WMV...
yanlei8158 Embedded System
[Reprint] FPGA Experience Summary
I reposted this article because I thought it was well written.   Timing is designed.   My boss has a background in working at Huawei and Junlong, so he naturally told us some things about Huawei and A...
suifeng654456 FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 339  1946  750  1384  1742  7  40  16  28  36 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号