INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4027B
flip-flops
Dual JK flip-flop
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
Dual JK flip-flop
DESCRIPTION
The HEF4027B is a dual JK flip-flop which is
edge-triggered and features independent set direct
(S
D
), clear direct (C
D
), clock (CP) inputs and outputs
(O,O). Data is accepted when CP is LOW, and transferred
to the output on the positive-going edge of the clock. The
active HIGH asynchronous clear-direct (C
D
) and set-direct
(S
D
) are independent and override the J, K, and CP inputs.
The outputs are buffered for best system performance.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
FUNCTION TABLES
INPUTS
S
D
H
L
H
C
D
L
H
H
CP
X
X
X
J
X
X
X
K
X
X
X
HEF4027B
flip-flops
OUTPUTS
O
H
L
H
O
L
H
H
INPUTS
S
D
L
L
L
L
Notes
C
D
L
L
L
L
CP
J
L
H
L
H
K
L
L
H
H
OUTPUTS
O
n
+
1
H
L
O
n
O
n
+
1
L
H
O
n
no change
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
= positive-going transition
O
n
+
1
= state after clock positive transition
PINNING
J,K
CP
S
D
C
D
O
O
synchronous inputs
clock input (L to H edge-triggered)
asynchronous set-direct input (active HIGH)
asynchronous clear-direct input (active HIGH)
true output
complement output
Fig.1 Functional diagram.
HEF4027BP(N):
HEF4027BD(F):
HEF4027BT(D):
16-lead DIL; plastic (SOT38-1)
16-lead DIL; ceramic (cerdip) (SOT74)
16-lead SO; plastic (SOT109-1)
( ): Package Designator North America
FAMILY DATA, I
DD
LIMITS category FLIP-FLOPS
See Family Specifications
Fig.2 Pinning diagram.
January 1995
2
Philips Semiconductors
Product specification
Dual JK flip-flop
HEF4027B
flip-flops
Fig.4
Waveforms showing set-up times, hold times and minimum clock pulse width. Set-up and hold times are
shown as positive values but may be specified as negative values.
Fig.5 Waveforms showing recovery times for S
D
and C
D
; minimum S
D
and C
D
pulse widths.
APPLICATION INFORMATION
Some examples of applications for the HEF4027B are:
•
Registers
•
Counters
•
Control circuits
January 1995
5
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