7024L70GGB datasheet, PDF - EEWORLD Datasheet

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7024L70GGB: DescriptionDual-Port SRAM, 4KX16, 70ns, CMOS, CPGA84; Categorystorage storage; File Size187KB，22 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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7024L70GGB Overview

Dual-Port SRAM, 4KX16, 70ns, CMOS, CPGA84

7024L70GGB Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
package instruction	PGA, PGA84M,11X11
Reach Compliance Code	compliant
Maximum access time	70 ns
I/O type	COMMON
JESD-30 code	S-CPGA-P84
JESD-609 code	e3
memory density	65536 bit
Memory IC Type	DUAL-PORT SRAM
memory width	16
Humidity sensitivity level	1
Number of functions	1
Number of ports	2
Number of terminals	84
word count	4096 words
character code	4000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	4KX16
Output characteristics	3-STATE
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Encapsulate equivalent code	PGA84M,11X11
Package shape	SQUARE
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	5 V
Certification status	Not Qualified
Filter level	MIL-PRF-38535
Maximum standby current	0.004 A
Minimum standby current	2 V
Maximum slew rate	0.25 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	MATTE TIN
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
Maximum time at peak reflow temperature	30
Base Number Matches	1

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HIGH-SPEED

4K x 16 DUAL-PORT

STATIC RAM

◆

IDT7024S/L

Features

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

– Military: 20/25/35/55/70ns (max.)

– Industrial: 55ns (max.)

– Commercial: 15/17/20/25/35/55ns (max.)

Low-power operation

– IDT7024S

Active: 750mW (typ.)

Standby: 5mW (typ.)

– IDT7024L

Active: 750mW (typ.)

Standby: 1mW (typ.)

Separate upper-byte and lower-byte control for multiplexed

bus compatibility

◆

IDT7024 easily expands data bus width to 32 bits or more

using the Master/Slave select when cascading more than

one device

M/S = H for

BUSY

output flag on Master

M/S = L for

BUSY

input on Slave

Interrupt Flag

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

Battery backup operation—2V data retention

TTL-compatible, single 5V (±10%) power supply

Available in 84-pin PGA, Flatpack, PLCC, and 100-pin Thin

Quad Flatpack

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Green parts availble, see ordering information

Functional Block Diagram

R/W

I/O

-I/O

15L

I/O

-I/O

BUSY

11L

(1,2)

I/O

-I/O

15R

I/O

Control

I/O

Control

I/O

-I/O

BUSY

Address

Decoder

(1,2)

MEMORY

ARRAY

Address

Decoder

11R

R/W

SEM

(2)

INT

NOTES:

1. (MASTER):

BUSY

is output; (SLAVE):

BUSY

is input.

BUSY

outputs and

INT

outputs are non-tri-stated push-pull.

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

R/W

SEM

INT

(2)

2740 drw 01

M/S

JUNE 2013

DSC 2740/14

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