INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4069UB
gates
Hex inverter
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
Hex inverter
DESCRIPTION
The HEF4069UB is a general purpose hex inverter. Each
of the six inverters is a single stage.
HEF4069UB
gates
Fig.2 Pinning diagram.
HEF4069UBP(N):
HEF4069UBD(F):
HEF4069UBT(D):
14-lead DIL; plastic
(SOT27-1)
14-lead DIL; ceramic (cerdip)
(SOT73)
14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
Fig.1 Functional diagram.
FAMILY DATA, I
DD
LIMITS category GATES
See Family Specifications for V
IH
/V
IL
unbuffered stages
Fig.3 Schematic diagram (one inverter).
January 1995
2
Philips Semiconductors
Product specification
Hex inverter
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
°C;
C
L
= 50 pF; input transition times
≤
20 ns
V
DD
V
Propagation delays
I
n
→
O
n
HIGH to LOW
LOW to HIGH
Output transition times
HIGH to LOW
5
10
15
5
10
15
5
10
15
5
LOW to HIGH
10
15
t
TLH
t
THL
t
PLH
t
PHL
SYMBOL
TYP. MAX.
45
20
15
40
20
15
60
30
20
60
30
20
90 ns
40 ns
25 ns
80 ns
40 ns
30 ns
120 ns
60 ns
40 ns
120 ns
60 ns
40 ns
HEF4069UB
gates
TYPICAL EXTRAPOLATION FORMULA
18 ns
+
(0,55 ns/pF) C
L
9 ns
+
(0,23 ns/pF) C
L
7 ns
+
(0,16 ns/pF) C
L
13 ns
+
(0,55 ns/pF) C
L
9 ns
+
(0,23 ns/pF) C
L
7 ns
+
(0,16 ns/pF) C
L
10 ns
+
(1,0 ns/pF) C
L
9 ns
+
(0,42 ns/pF) C
L
6 ns
+
(0,28 ns/pF) C
L
10 ns
+
(1,0 ns/pF) C
L
9 ns
+
(0,42 ns/pF) C
L
6 ns
+
(0,28 ns/pF) C
L
V
DD
V
Dynamic power
dissipation per
package (P)
5
10
15
TYPICAL FORMULA FOR P (µW)
600 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
4 000 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
22 000 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
where
f
i
= input freq. (MHz)
f
o
= output freq. (MHz)
C
L
= load capacitance (pF)
∑
(f
o
C
L
) = sum of outputs
V
DD
= supply voltage (V)
January 1995
3
Philips Semiconductors
Product specification
Hex inverter
HEF4069UB
gates
Fig.4
Typical transfer characteristics;
___ V
O
;
_ _ _ I
D
(drain current);
I
O
= 0; V
DD
= 5 V.
Fig.5
Typical transfer characteristics;
___ V
O
;
_ _ _ I
D
(drain current);
I
O
= 0; V
DD
= 10 V.
Fig.6
Typical transfer characteristics;
___ V
O
;
_ _ _ I
D
(drain current);
I
O
= 0; V
DD
= 15 V.
January 1995
4
Philips Semiconductors
Product specification
Hex inverter
APPLICATION INFORMATION
Some examples of applications for the HEF4069UB are shown below.
HEF4069UB
gates
In Fig.7 an astable relaxation oscillator is given. The oscillation frequency is mainly determined by R1C1, provided
R1 << R2 and R2C2 << R1C1.
(a)
(b)
The function of R2 is to minimize the influence of the forward voltage across
the protection diodes on the frequency; C2 is a stray (parasitic) capacitance.
The period T
p
is given by T
p
= T
1
+ T
2
, in which
V
DD
+
V
ST
2 V
DD
–
V
ST
-
-
T
1
=
R1C1 In
----------------------------
and T
2
=
R1C1 In
---------------------------------
where
V
ST
V
DD
–
V
ST
V
ST
is the signal threshold level of the inverter. The period is fairly independent
of V
DD
, V
ST
and temperature. The duty factor, however, is influenced by V
ST
.
Fig.7
(a) Astable relaxation oscillator using two HEF4069UB inverters; the diodes may be BAW62; C2 is a
parasitic capacitance. (b) Waveforms at the points marked A, B, C and D in the circuit diagram.
January 1995
5
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