INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4510B
MSI
BCD up/down counter
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
BCD up/down counter
DESCRIPTION
The HEF4510B is an edge-triggered synchronous
up/down BCD counter with a clock input (CP), an up/down
count control input (UP/DN), an active LOW count enable
input (CE), an asynchronous active HIGH parallel load
input (PL), four parallel inputs (P
0
to P
3
), four parallel
outputs (O
0
to O
3
), an active LOW terminal count output
(TC), and an overriding asynchronous master reset input
(MR).
Information on P
0
to P
3
is loaded into the counter while PL
is HIGH, independent of all other input conditions except
the MR input, which must be LOW. With PL LOW, the
counter changes on the LOW to HIGH transition of CP if
CE is LOW. UP/DN determines the direction of the count,
HIGH for counting up, LOW for counting down. When
counting up, TC is LOW when O
0
and O
3
are HIGH and
CE is LOW. When counting down, TC is LOW when O
0
to
O
3
and CE are LOW. A HIGH on MR resets the counter
(O
0
to O
3
= LOW) independent of all other input
conditions.
HEF4510B
MSI
Fig.1 Functional diagram.
PINNING
HEF4510BP(N):
HEF4510BD(F):
HEF4510BT(D):
16-lead DIL; plastic
(SOT38-1)
16-lead DIL; ceramic (cerdip)
(SOT74)
16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
UP/DN
MR
TC
O
0
to O
3
PL
P
0
to P
3
CE
CP
parallel load input (active HIGH)
parallel inputs
count enable input (active LOW)
clock pulse input (LOW to HIGH,
edge triggered)
up/down count control input
master reset input
terminal count output (active LOW)
parallel outputs
FAMILY DATA, I
DD
LIMITS category MSI
See Family Specifications
Fig.2 Pinning diagram.
January 1995
2
Philips Semiconductors
Product specification
BCD up/down counter
FUNCTION TABLE
MR
L
L
L
L
H
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
= positive-going transition
PL
H
L
L
L
X
UP/DN
X
X
L
H
X
CE
X
H
L
L
X
X
CP
X
X
MODE
parallel load
no change
count down
count up
reset
HEF4510B
MSI
Fig.5 State diagram.
Logic equation for terminal count:
TC
=
CE
⋅ { (
UP/DN
) ⋅
O
0
⋅
O
3
+
(
UP
⁄
DN
) ⋅
O
0
⋅
O
1
⋅
O
2
⋅
O
3
}
A.C. CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
°C;
input transition times
≤
20 ns
V
DD
V
Dynamic power
dissipation per
package (P)
5
10
15
TYPICAL FORMULA FOR P (µW)
1000 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
4500 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
11 200 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
where
f
i
= input freq. (MHz)
f
o
= output freq. (MHz)
C
L
= load capacitance (pF)
∑
(f
o
C
L
) = sum of outputs
V
DD
= supply voltage (V)
January 1995
5
Embedded System
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